forked from M-Labs/artiq
compiler: enabled vectorize option
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@ -28,6 +28,7 @@ Highlights:
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- SERDES TTL inputs can now detect edges on pulses that are shorter
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than the RTIO period (https://github.com/m-labs/artiq/issues/1432)
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- Improved performance for kernel RPC involving list and array.
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- Improved performance for computation involving loops.
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* Coredevice SI to mu conversions now always return valid codes, or raise a ``ValueError``.
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* Zotino now exposes ``voltage_to_mu()``
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* ``ad9910``: The maximum amplitude scale factor is now ``0x3fff`` (was ``0x3ffe``
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@ -105,7 +105,11 @@ class Target:
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return llmachine
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def optimize(self, llmodule):
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pmb = llvm.create_pass_manager_builder()
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pmb.slp_vectorize = True
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pmb.loop_vectorize = True
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llpassmgr = llvm.create_module_pass_manager()
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pmb.populate(llpassmgr)
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# Register our alias analysis passes.
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llpassmgr.add_basic_alias_analysis_pass()
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