From 627504b60e09f9380c2c327928593a205a8a6b0b Mon Sep 17 00:00:00 2001 From: mwojcik Date: Tue, 10 Jan 2023 16:54:45 +0800 Subject: [PATCH] test_dma: remove redundant clock --- artiq/gateware/test/rtio/test_dma.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/test/rtio/test_dma.py b/artiq/gateware/test/rtio/test_dma.py index 692e5be17..54b996b4f 100644 --- a/artiq/gateware/test/rtio/test_dma.py +++ b/artiq/gateware/test/rtio/test_dma.py @@ -203,11 +203,11 @@ class TestDMA(unittest.TestCase): run_simulation(tb[32], {"sys": [ do_dma(tb[32].dut, 0), monitor(32), (None for _ in range(70)), - ]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8}) + ]}, {"sys": 8, "rio": 8, "rio_phy": 8}) run_simulation(tb[64], {"sys": [ do_dma(tb[64].dut, 0), monitor(64), (None for _ in range(70)), - ]}, {"sys": 8, "sys": 8, "rio": 8, "rio_phy": 8}) + ]}, {"sys": 8, "rio": 8, "rio_phy": 8}) correct_changes = [(timestamp + 11, channel) for channel, timestamp, _, _ in test_writes_full_stack]