From 626075cbc1dbf8d24ee451404955ebce93d1f8b9 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 23 Jan 2018 09:49:23 +0800 Subject: [PATCH] gtp_7series: simplify TX clocking --- artiq/gateware/drtio/transceiver/gtp_7series.py | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/artiq/gateware/drtio/transceiver/gtp_7series.py b/artiq/gateware/drtio/transceiver/gtp_7series.py index 797c256bb..7493343be 100644 --- a/artiq/gateware/drtio/transceiver/gtp_7series.py +++ b/artiq/gateware/drtio/transceiver/gtp_7series.py @@ -175,16 +175,7 @@ class GTPSingle(Module): self.sync += tx_reset_deglitched.eq(~tx_init.done) self.clock_domains.cd_rtio_tx = ClockDomain() if mode == "master": - txoutclk_bufg = Signal() - txoutclk_bufr = Signal() - tx_bufr_div = 150.e6/rtio_clk_freq - assert tx_bufr_div == int(tx_bufr_div) - self.specials += [ - Instance("BUFG", i_I=self.txoutclk, o_O=txoutclk_bufg), - Instance("BUFR", i_I=txoutclk_bufg, o_O=txoutclk_bufr, - i_CE=1, p_BUFR_DIVIDE=str(int(tx_bufr_div))), - Instance("BUFG", i_I=txoutclk_bufr, o_O=self.cd_rtio_tx.clk) - ] + self.specials += Instance("BUFG", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk) self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched) # rx clocking