forked from M-Labs/artiq
artiq_flash: fix sayma amc tap/pld index
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parent
e16ab69f01
commit
62320432a5
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@ -109,11 +109,11 @@ class ProgrammerJtagSpi7(Programmer):
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preinit_commands)
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self.init()
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def load(self, bitfile):
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self.prog.append("pld load 0 " + bitfile)
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def load(self, bitfile, pld=0):
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self.prog.append("pld load {} {{{}}}".format(pld, bitfile))
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def proxy(self, proxy_bitfile):
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self.prog.append("jtagspi_init 0 {{{}}}".format(proxy_bitfile))
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def proxy(self, proxy_bitfile, pld=0):
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self.prog.append("jtagspi_init {} {{{}}}".format(pld, proxy_bitfile))
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def flash_binary(self, flashno, address, filename):
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# jtagspi_program supports only one flash
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@ -143,9 +143,9 @@ class ProgrammerSayma(Programmer):
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"adapter_khz 5000",
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"transport select jtag",
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"source [find cpld/xilinx-xc7.cfg]",
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"source [find cpld/xilinx-xc7.cfg]", # tap 0, pld 0
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"set CHIP XCKU040",
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"source [find cpld/xilinx-xcu.cfg]",
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"source [find cpld/xilinx-xcu.cfg]", # tap 1, pld 1
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"set XILINX_USER1 0x02",
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"set XILINX_USER2 0x03",
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@ -156,14 +156,12 @@ class ProgrammerSayma(Programmer):
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]
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self.init()
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def load(self, bitfile):
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self.prog.append("pld load 0 " + bitfile)
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def load(self, bitfile, pld=1):
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self.prog.append("pld load {} {{{}}}".format(pld, bitfile))
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def proxy(self, proxy_bitfile):
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self.prog += [
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"pld load 0 " + proxy_bitfile,
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"reset halt"
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]
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def proxy(self, proxy_bitfile, pld=1):
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self.load(proxy_bitfile, pld)
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self.prog.append("reset halt")
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def flash_binary(self, flashno, address, filename):
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self.prog += [
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