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pipistrello: basesoc, cleanup

This commit is contained in:
Robert Jördens 2015-04-11 15:32:43 -06:00
parent 4c10182c9f
commit 6217cf5392
1 changed files with 26 additions and 20 deletions
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46
soc/targets/artiq_pipistrello.py
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@ -30,21 +30,14 @@ class _RTIOCRG(Module, AutoCSR):
i_FREEZEDCM=0, i_FREEZEDCM=0,
i_RST=ResetSignal()) i_RST=ResetSignal())
rtio_external_clk = platform.request("dds_clock") self.rtio_external_clk = platform.request("dds_clock")
platform.add_period_constraint(rtio_external_clk, 8.0) platform.add_period_constraint(self.rtio_external_clk, 8.0)
self.specials += Instance("BUFGMUX", self.specials += Instance("BUFGMUX",
i_I0=rtio_internal_clk, i_I0=rtio_internal_clk,
i_I1=rtio_external_clk, i_I1=self.rtio_external_clk,
i_S=self._clock_sel.storage, i_S=self._clock_sel.storage,
o_O=self.cd_rtio.clk) o_O=self.cd_rtio.clk)
platform.add_platform_command("""
NET "{rtio_clk}" TNM_NET = "GRPrtio_clk";
NET "sys_clk" TNM_NET = "GRPsys_clk";
TIMESPEC "TSfix_ise1" = FROM "GRPrtio_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
""", rtio_clk=rtio_internal_clk)
class _Peripherals(BaseSoC): class _Peripherals(BaseSoC):
csr_map = { csr_map = {
@ -53,8 +46,8 @@ class _Peripherals(BaseSoC):
} }
csr_map.update(BaseSoC.csr_map) csr_map.update(BaseSoC.csr_map)
mem_map = { mem_map = {
"rtio": 0x20000000, # (shadow @0xa0000000) "rtio": 0x20000000, # (shadow @0xa0000000)
"dds": 0x50000000, # (shadow @0xd0000000) "dds": 0x50000000, # (shadow @0xd0000000)
} }
mem_map.update(BaseSoC.mem_map) mem_map.update(BaseSoC.mem_map)
@ -107,6 +100,12 @@ class _Peripherals(BaseSoC):
self.submodules.rtiocrg = _RTIOCRG(platform) self.submodules.rtiocrg = _RTIOCRG(platform)
self.submodules.rtio = rtio.RTIO(rtio_channels, self.submodules.rtio = rtio.RTIO(rtio_channels,
clk_freq=125000000) clk_freq=125000000)
platform.add_platform_command("""
NET "{rtio_ext_clk}" TNM_NET = "GRPrtio_ext_clk";
NET "{sys_clk}" TNM_NET = "GRPsys_clk";
TIMESPEC "TSfix_ise1" = FROM "GRPrtio_ext_clk" TO "GRPsys_clk" TIG;
TIMESPEC "TSfix_ise2" = FROM "GRPsys_clk" TO "GRPrtio_ext_clk" TIG;
""", rtio_ext_clk=self.rtiocrg.rtio_external_clk, sys_clk=self.crg.cd_sys.clk)
dds_pads = platform.request("dds") dds_pads = platform.request("dds")
self.submodules.dds = ad9858.AD9858(dds_pads) self.submodules.dds = ad9858.AD9858(dds_pads)
@ -120,18 +119,20 @@ class UP(_Peripherals):
rtio_csrs = self.rtio.get_csrs() rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs) self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus) self.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs) self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
rtio_csrs)
self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus) self.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus)
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4) self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
class AMP(_Peripherals): class AMP(_Peripherals):
csr_map = { csr_map = {
"kernel_cpu": 14 "kernel_cpu": 14
} }
csr_map.update(_Peripherals.csr_map) csr_map.update(_Peripherals.csr_map)
mem_map = { mem_map = {
"mailbox": 0x70000000 # (shadow @0xf0000000) "mailbox": 0x70000000 # (shadow @0xf0000000)
} }
mem_map.update(_Peripherals.mem_map) mem_map.update(_Peripherals.mem_map)
@ -141,16 +142,21 @@ class AMP(_Peripherals):
self.submodules.kernel_cpu = amp.KernelCPU( self.submodules.kernel_cpu = amp.KernelCPU(
platform, self.sdram.crossbar.get_master()) platform, self.sdram.crossbar.get_master())
self.submodules.mailbox = amp.Mailbox() self.submodules.mailbox = amp.Mailbox()
self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i1) self.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]), self.mailbox.i2) self.mailbox.i1)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["mailbox"]),
self.mailbox.i2)
rtio_csrs = self.rtio.get_csrs() rtio_csrs = self.rtio.get_csrs()
self.submodules.rtiowb = wbgen.Bank(rtio_csrs) self.submodules.rtiowb = wbgen.Bank(rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]), self.rtiowb.bus) self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["rtio"]),
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32, rtio_csrs) self.rtiowb.bus)
self.add_csr_region("rtio", self.mem_map["rtio"] + 0x80000000, 32,
rtio_csrs)
self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]), self.dds.bus) self.kernel_cpu.add_wb_slave(mem_decoder(self.mem_map["dds"]),
self.kernel_cpu.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4) self.dds.bus)
self.add_memory_region("dds", self.mem_map["dds"] + 0x80000000, 64*4)
default_subtarget = UP default_subtarget = UP