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kc705: 16 TTLs

This commit is contained in:
Sebastien Bourdeauducq 2015-04-03 15:57:25 +08:00
parent fb91955260
commit 5f7161a7de
1 changed files with 1 additions and 1 deletions
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2
soc/targets/artiq_kc705.py
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@ -90,7 +90,7 @@ class _ARTIQSoCPeripherals(BaseSoC):
platform.request("ttl_h_tx_en").eq(1) platform.request("ttl_h_tx_en").eq(1)
] ]
rtio_ins = [platform.request("pmt") for i in range(2)] rtio_ins = [platform.request("pmt") for i in range(2)]
rtio_outs = [platform.request("ttl", i) for i in range(6)] + [fud] rtio_outs = [platform.request("ttl", i) for i in range(16)] + [fud]
self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys) self.submodules.rtiocrg = _RTIOCRG(platform, self.crg.pll_sys)
self.submodules.rtiophy = rtio.phy.SimplePHY( self.submodules.rtiophy = rtio.phy.SimplePHY(