From 5f20d79408fb6ee0fc81c712d4a1f44700f625b3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Wed, 5 Sep 2018 14:00:09 +0800 Subject: [PATCH] drtio: add timeout on satellite internal CRI buffer space request --- artiq/firmware/satman/main.rs | 5 ++++- artiq/gateware/drtio/rt_errors_satellite.py | 3 ++- artiq/gateware/drtio/rt_packet_satellite.py | 10 ++++++++++ artiq/gateware/test/drtio/test_full_stack.py | 2 +- 4 files changed, 17 insertions(+), 3 deletions(-) diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs index 849901e88..85143253d 100644 --- a/artiq/firmware/satman/main.rs +++ b/artiq/firmware/satman/main.rs @@ -210,6 +210,9 @@ fn process_errors() { error!("received truncated packet"); } if errors & 4 != 0 { + error!("timeout attempting to get buffer space from CRI") + } + if errors & 8 != 0 { let channel; let timestamp_event; let timestamp_counter; @@ -221,7 +224,7 @@ fn process_errors() { error!("write underflow, channel={}, timestamp={}, counter={}, slack={}", channel, timestamp_event, timestamp_counter, timestamp_event-timestamp_counter); } - if errors & 8 != 0 { + if errors & 16 != 0 { error!("write overflow"); } unsafe { diff --git a/artiq/gateware/drtio/rt_errors_satellite.py b/artiq/gateware/drtio/rt_errors_satellite.py index 764365730..2bf190a0f 100644 --- a/artiq/gateware/drtio/rt_errors_satellite.py +++ b/artiq/gateware/drtio/rt_errors_satellite.py @@ -8,7 +8,7 @@ from artiq.gateware.rtio.cdc import BlindTransfer class RTErrorsSatellite(Module, AutoCSR): def __init__(self, rt_packet, tsc, cri, async_errors): - self.protocol_error = CSR(4) + self.protocol_error = CSR(5) self.underflow_channel = CSRStatus(16) self.underflow_timestamp_event = CSRStatus(64) self.underflow_timestamp_counter = CSRStatus(64) @@ -68,6 +68,7 @@ class RTErrorsSatellite(Module, AutoCSR): error_csr(self.protocol_error, (rt_packet.unknown_packet_type, False, None, None), (rt_packet.packet_truncated, False, None, None), + (rt_packet.buffer_space_timeout, False, None, None), (underflow, True, underflow_error_cri, underflow_error_csr), (overflow, True, None, None) ) diff --git a/artiq/gateware/drtio/rt_packet_satellite.py b/artiq/gateware/drtio/rt_packet_satellite.py index 4760e11ac..1656f41cd 100644 --- a/artiq/gateware/drtio/rt_packet_satellite.py +++ b/artiq/gateware/drtio/rt_packet_satellite.py @@ -2,6 +2,7 @@ from migen import * from migen.genlib.fsm import * +from migen.genlib.misc import WaitTimer from artiq.gateware.rtio import cri from artiq.gateware.drtio.rt_serializer import * @@ -13,6 +14,7 @@ class RTPacketSatellite(Module): self.unknown_packet_type = Signal() self.packet_truncated = Signal() + self.buffer_space_timeout = Signal() self.tsc_load = Signal() self.tsc_load_value = Signal(64) @@ -105,6 +107,9 @@ class RTPacketSatellite(Module): ongoing_packet = Signal() self.sync += ongoing_packet.eq(ongoing_packet_next) + timeout_counter = WaitTimer(8191) + self.submodules += timeout_counter + rx_fsm.act("INPUT", If(rx_dp.frame_r, rx_dp.packet_buffer_load.eq(1), @@ -149,6 +154,11 @@ class RTPacketSatellite(Module): NextState("BUFFER_SPACE") ) rx_fsm.act("BUFFER_SPACE", + timeout_counter.wait.eq(1), + If(timeout_counter.done, + self.buffer_space_timeout.eq(1), + NextState("INPUT") + ), If(self.cri.o_buffer_space_valid, buffer_space_set.eq(1), buffer_space_update.eq(1), diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py index eafb438c1..69f89b094 100644 --- a/artiq/gateware/test/drtio/test_full_stack.py +++ b/artiq/gateware/test/drtio/test_full_stack.py @@ -236,7 +236,7 @@ class TestFullStack(unittest.TestCase): errors = yield from saterr.protocol_error.read() underflow_channel = yield from saterr.underflow_channel.read() underflow_timestamp_event = yield from saterr.underflow_timestamp_event.read() - self.assertEqual(errors, 4) # write underflow + self.assertEqual(errors, 8) # write underflow self.assertEqual(underflow_channel, 42) self.assertEqual(underflow_timestamp_event, 100) yield from saterr.protocol_error.write(errors)