diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
index f9b94e26c..6312170c9 100755
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@@ -365,6 +365,8 @@ class MasterBase(MiniSoC, AMPSoC):
         self.csr_devices.append("rtio_analyzer")
 
     def add_eem_drtio(self, eem_drtio_channels):
+        # Must be called before invoking add_rtio() to construct the CRI
+        # interconnect properly
         self.submodules.eem_transceiver = eem_serdes.EEMSerdes(self.platform, eem_drtio_channels)
         self.csr_devices.append("eem_transceiver")
         self.config["HAS_DRTIO_EEM"] = None