forked from M-Labs/artiq
kasli: implement multi-link DRTIO on SFP1 and SFP2 of master
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2f9d01295c
commit
5d81877b34
@ -337,25 +337,39 @@ class Master(MiniSoC, AMPSoC):
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self.config["SI5324_AS_SYNTHESIZER"] = None
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.comb += platform.request("sfp_ctl", 2).tx_disable.eq(0)
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sfp_ctl = [platform.request("sfp_ctl", i) for i in range(1, 3)]
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self.comb += [sc.tx_disable.eq(0) for sc in sfp_ctl]
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self.submodules.drtio_transceiver = gtp_7series.GTP(
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qpll_channel=self.drtio_qpll_channel,
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data_pads=[platform.request("sfp", 2)],
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data_pads=[platform.request("sfp", i) for i in range(1, 3)],
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sys_clk_freq=self.clk_freq,
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rtio_clk_freq=rtio_clk_freq)
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self.csr_devices.append("drtio_transceiver")
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self.sync += self.disable_si5324_ibuf.eq(
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~self.drtio_transceiver.stable_clkin.storage)
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self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
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DRTIOMaster(self.drtio_transceiver.channels[0]))
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self.csr_devices.append("drtio0")
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self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
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self.drtio0.aux_controller.bus)
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self.add_memory_region("drtio0_aux", self.mem_map["drtio_aux"] | self.shadow_base, 0x800)
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drtio_csr_group = []
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drtio_memory_group = []
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drtio_cri = []
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for i in range(2):
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core_name = "drtio" + str(i)
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memory_name = "drtio" + str(i) + "_aux"
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drtio_csr_group.append(core_name)
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drtio_memory_group.append(memory_name)
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core = ClockDomainsRenamer({"rtio_rx": "rtio_rx" + str(i)})(
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DRTIOMaster(self.drtio_transceiver.channels[i]))
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setattr(self.submodules, core_name, core)
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drtio_cri.append(core.cri)
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self.csr_devices.append(core_name)
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memory_address = self.mem_map["drtio_aux"] + 0x800*i
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self.add_wb_slave(memory_address, 0x800,
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core.aux_controller.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_memory_group("drtio_aux", drtio_memory_group)
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rtio_clk_period = 1e9/rtio_clk_freq
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for gtp in self.drtio_transceiver.gtps:
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@ -369,9 +383,10 @@ class Master(MiniSoC, AMPSoC):
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phy = ttl_simple.Output(platform.request("user_led", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = ttl_simple.Output(platform.request("sfp_ctl", 1).led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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for sc in sfp_ctl:
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phy = ttl_simple.Output(sc.led)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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self.config["HAS_RTIO_LOG"] = None
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self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
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rtio_channels.append(rtio.LogChannel())
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@ -389,7 +404,7 @@ class Master(MiniSoC, AMPSoC):
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri, self.drtio0.cri])
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[self.rtio_core.cri] + drtio_cri)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.cri_con.switch.slave,
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