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sayma_rtm2: si5324_clkout -> cdr_clk_clean

This commit is contained in:
Sebastien Bourdeauducq 2019-03-23 13:48:36 +08:00
parent 560849e693
commit 5d31cf2268
2 changed files with 2 additions and 2 deletions
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2
artiq/gateware/targets/sayma_rtm.py
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@ -195,7 +195,7 @@ class SaymaRTM(Module):
sysref_pads = platform.request("rtm_master_aux_clk") sysref_pads = platform.request("rtm_master_aux_clk")
elif hw_rev == "v2.0": elif hw_rev == "v2.0":
# https://github.com/sinara-hw/Sayma_RTM/issues/68 # https://github.com/sinara-hw/Sayma_RTM/issues/68
rtio_clock_pads = platform.request("si5324_clkout_fabric") rtio_clock_pads = platform.request("cdr_clk_clean_fabric")
sysref_pads = platform.request("rtm_fpga_sysref", 1) # use odd-numbered 7043 output sysref_pads = platform.request("rtm_fpga_sysref", 1) # use odd-numbered 7043 output
else: else:
raise NotImplementedError raise NotImplementedError

2
artiq/gateware/targets/sayma_rtm_drtio.py
View File

@ -82,7 +82,7 @@ class _SatelliteBase(BaseSoC):
disable_si5324_ibuf = Signal(reset=1) disable_si5324_ibuf = Signal(reset=1)
disable_si5324_ibuf.attr.add("no_retiming") disable_si5324_ibuf.attr.add("no_retiming")
si5324_clkout = platform.request("si5324_clkout") si5324_clkout = platform.request("cdr_clk_clean")
si5324_clkout_buf = Signal() si5324_clkout_buf = Signal()
self.specials += Instance("IBUFDS_GTE2", self.specials += Instance("IBUFDS_GTE2",
i_CEB=disable_si5324_ibuf, i_CEB=disable_si5324_ibuf,