From 5d31cf226817d5a029fda663055380f846a27fa3 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 23 Mar 2019 13:48:36 +0800 Subject: [PATCH] sayma_rtm2: si5324_clkout -> cdr_clk_clean --- artiq/gateware/targets/sayma_rtm.py | 2 +- artiq/gateware/targets/sayma_rtm_drtio.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_rtm.py b/artiq/gateware/targets/sayma_rtm.py index 48097d3b9..0f4e23d7b 100755 --- a/artiq/gateware/targets/sayma_rtm.py +++ b/artiq/gateware/targets/sayma_rtm.py @@ -195,7 +195,7 @@ class SaymaRTM(Module): sysref_pads = platform.request("rtm_master_aux_clk") elif hw_rev == "v2.0": # https://github.com/sinara-hw/Sayma_RTM/issues/68 - rtio_clock_pads = platform.request("si5324_clkout_fabric") + rtio_clock_pads = platform.request("cdr_clk_clean_fabric") sysref_pads = platform.request("rtm_fpga_sysref", 1) # use odd-numbered 7043 output else: raise NotImplementedError diff --git a/artiq/gateware/targets/sayma_rtm_drtio.py b/artiq/gateware/targets/sayma_rtm_drtio.py index 69a608aca..d6247652d 100755 --- a/artiq/gateware/targets/sayma_rtm_drtio.py +++ b/artiq/gateware/targets/sayma_rtm_drtio.py @@ -82,7 +82,7 @@ class _SatelliteBase(BaseSoC): disable_si5324_ibuf = Signal(reset=1) disable_si5324_ibuf.attr.add("no_retiming") - si5324_clkout = platform.request("si5324_clkout") + si5324_clkout = platform.request("cdr_clk_clean") si5324_clkout_buf = Signal() self.specials += Instance("IBUFDS_GTE2", i_CEB=disable_si5324_ibuf,