forked from M-Labs/artiq
test: add regression tests for master.databases.DeviceDB
Signed-off-by: Etienne Wodey <wodey@iqo.uni-hannover.de>
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"""Test device DB interface"""
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import unittest
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import tempfile
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from artiq.master.databases import DeviceDB
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from artiq.tools import file_import
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DUMMY_DDB_FILE = """
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device_db = {
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"core": {
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"type": "local",
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"module": "artiq.coredevice.core",
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"class": "Core",
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"arguments": {"host": "::1", "ref_period": 1e-09},
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},
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"core-alias": "core",
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"unresolved-alias": "dummy",
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}
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"""
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class TestInvalidDeviceDB(unittest.TestCase):
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def test_no_device_db_in_file(self):
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with tempfile.NamedTemporaryFile(mode="w+", suffix=".py") as f:
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print("", file=f, flush=True)
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with self.assertRaisesRegex(KeyError, "device_db"):
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DeviceDB(f.name)
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class TestDeviceDB(unittest.TestCase):
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def setUp(self):
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self.ddb_file = tempfile.NamedTemporaryFile(mode="w+", suffix=".py")
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print(DUMMY_DDB_FILE, file=self.ddb_file, flush=True)
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self.ddb = DeviceDB(self.ddb_file.name)
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def test_get(self):
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core = self.ddb.get("core")
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self.assertEqual(core["class"], "Core")
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def test_get_alias(self):
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with self.assertRaises(TypeError): # str indexing on str
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self.ddb.get("core-alias")["class"]
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self.assertEqual(
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self.ddb.get("core-alias", resolve_alias=True), self.ddb.get("core")
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)
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def test_get_unresolved_alias(self):
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with self.assertRaisesRegex(KeyError, "dummy"):
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self.ddb.get("unresolved-alias", resolve_alias=True)
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def test_update(self):
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with self.assertRaises(KeyError):
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self.ddb.get("core_log")
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update = """
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device_db["core_log"] = {
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"type": "controller",
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"host": "::1",
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"port": 1068,
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"command": "aqctl_corelog -p {port} --bind {bind} ::1",
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}"""
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print(update, file=self.ddb_file, flush=True)
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self.ddb.scan()
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self.assertEqual(self.ddb.get("core_log")["type"], "controller")
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def test_get_ddb(self):
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ddb = self.ddb.get_device_db()
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raw = file_import(self.ddb_file.name).device_db
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self.assertEqual(ddb, raw)
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