From 5bcd40ff59d9b2048875f9f6ba9f8ee31e6dbf4b Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 12 Sep 2018 17:30:55 +0800
Subject: [PATCH] cri: fix routing table depth

---
 artiq/gateware/rtio/cri.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/gateware/rtio/cri.py b/artiq/gateware/rtio/cri.py
index 18ca1956b..0ed0d50e2 100644
--- a/artiq/gateware/rtio/cri.py
+++ b/artiq/gateware/rtio/cri.py
@@ -130,7 +130,7 @@ class CRIDecoder(Module, AutoCSR):
         selected = Signal(slave_bits)
 
         if enable_routing:
-            self.specials.routing_table = Memory(slave_bits, 8)
+            self.specials.routing_table = Memory(slave_bits, 256)
 
             rtp_csr = self.routing_table.get_port(write_capable=True)
             self.specials += rtp_csr