diff --git a/artiq/coredevice/ad9910.py b/artiq/coredevice/ad9910.py index e2600d6ac..39d2adfa6 100644 --- a/artiq/coredevice/ad9910.py +++ b/artiq/coredevice/ad9910.py @@ -332,7 +332,7 @@ class AD9910: self.bus.write(0) hi = self.bus.read() lo = self.bus.read() - return (int64(hi) << int64(32)) | int64(lo) + return (int64(hi) << 32) | int64(lo) @kernel def write64(self, addr: int32, data_high: int32, data_low: int32): @@ -633,8 +633,8 @@ class AD9910: data = int64(self.read64(_AD9910_REG_PROFILE0 + profile)) # Extract and return fields ftw = int32(data) - pow_ = int32(data >> int64(32)) & 0xffff - asf = int32(data >> int64(48)) & 0x3fff + pow_ = int32(data >> 32) & 0xffff + asf = int32(data >> 48) & 0x3fff return ftw, pow_, asf @kernel diff --git a/artiq/coredevice/ad9912.py b/artiq/coredevice/ad9912.py index 44b2109cb..651d051c5 100644 --- a/artiq/coredevice/ad9912.py +++ b/artiq/coredevice/ad9912.py @@ -189,7 +189,7 @@ class AD9912: self.bus.write((AD9912_POW1 << 16) | (3 << 29)) self.bus.set_config_mu(SPI_CONFIG, 32, SPIT_DDS_WR, self.chip_select) - self.bus.write((pow_ << 16) | (int32(ftw >> int64(32)) & 0xffff)) + self.bus.write((pow_ << 16) | (int32(ftw >> 32) & 0xffff)) self.bus.set_config_mu(SPI_CONFIG | SPI_END, 32, SPIT_DDS_WR, self.chip_select) self.bus.write(int32(ftw)) @@ -209,7 +209,7 @@ class AD9912: self.core.break_realtime() # Regain slack to perform second read low = self.read(AD9912_FTW3, 4) # Extract and return fields - ftw = (int64(high & 0xffff) << int64(32)) | (int64(low) & int64(0xffffffff)) + ftw = (int64(high & 0xffff) << 32) | (int64(low) & int64(0xffffffff)) pow_ = (high >> 16) & 0x3fff return ftw, pow_ @@ -219,7 +219,7 @@ class AD9912: frequency. """ return round64(self.ftw_per_hz * frequency) & ( - (int64(1) << int64(48)) - int64(1)) + (int64(1) << 48) - int64(1)) @portable def ftw_to_frequency(self, ftw: int64) -> float: diff --git a/artiq/coredevice/adf5356.py b/artiq/coredevice/adf5356.py index 8376997b6..11af0d6a0 100644 --- a/artiq/coredevice/adf5356.py +++ b/artiq/coredevice/adf5356.py @@ -201,7 +201,7 @@ class ADF5356: # select minimal output divider rf_div_sel = 0 while freq < ADF5356_MIN_VCO_FREQ: - freq <<= int64(1) + freq <<= 1 rf_div_sel += 1 if (1 << rf_div_sel) > 64: @@ -274,7 +274,7 @@ class ADF5356: # calculate PLL at f_pfd/2 n, frac1, (frac2_msb, frac2_lsb), (mod2_msb, mod2_lsb) = calculate_pll( - self.f_vco(), f_pfd >> int64(1) + self.f_vco(), f_pfd >> 1 ) self.core.delay(200. * us) # Slack @@ -596,8 +596,8 @@ def calculate_pll(f_vco: int64, f_pfd: int64) -> tuple[int32, int32, tuple[int32 mod2 = f_pfd while mod2 > int64(ADF5356_MAX_MODULUS2): - mod2 >>= int64(1) - frac2 >>= int64(1) + mod2 >>= 1 + frac2 >>= 1 gcd_div = gcd(frac2, mod2) mod2 //= gcd_div diff --git a/artiq/coredevice/shuttler.py b/artiq/coredevice/shuttler.py index cc75dc9b0..a9d8596ef 100644 --- a/artiq/coredevice/shuttler.py +++ b/artiq/coredevice/shuttler.py @@ -176,11 +176,11 @@ class DCBias: a1, a1 >> 16, int32(a2 & int64(0xFFFF)), - int32((a2 >> int64(16)) & int64(0xFFFF)), - int32((a2 >> int64(32)) & int64(0xFFFF)), + int32((a2 >> 16) & int64(0xFFFF)), + int32((a2 >> 32) & int64(0xFFFF)), int32(a3 & int64(0xFFFF)), - int32((a3 >> int64(16)) & int64(0xFFFF)), - int32((a3 >> int64(32)) & int64(0xFFFF)), + int32((a3 >> 16) & int64(0xFFFF)), + int32((a3 >> 32) & int64(0xFFFF)), ] for i in range(len(coef_words)): @@ -269,11 +269,11 @@ class DDS: b1, b1 >> 16, int32(b2 & int64(0xFFFF)), - int32((b2 >> int64(16)) & int64(0xFFFF)), - int32((b2 >> int64(32)) & int64(0xFFFF)), + int32((b2 >> 16) & int64(0xFFFF)), + int32((b2 >> 32) & int64(0xFFFF)), int32(b3 & int64(0xFFFF)), - int32((b3 >> int64(16)) & int64(0xFFFF)), - int32((b3 >> int64(32)) & int64(0xFFFF)), + int32((b3 >> 16) & int64(0xFFFF)), + int32((b3 >> 32) & int64(0xFFFF)), c0, c1, c1 >> 16,