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rtio/ttl_serdes_7series: use recommended OSERDES T configuration

This commit is contained in:
Sebastien Bourdeauducq 2015-07-27 10:50:50 +08:00
parent d3f05e414a
commit 5b50f5fe05
1 changed files with 3 additions and 3 deletions
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6
artiq/gateware/rtio/phy/ttl_serdes_7series.py
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@ -12,9 +12,9 @@ class _OSERDESE2_8X(Module):
# # # # # #
o = self.o o = self.o
self.specials += Instance("OSERDESE2", p_DATA_RATE_OQ="DDR", self.specials += Instance("OSERDESE2",
p_DATA_RATE_TQ="DDR", p_DATA_WIDTH=8, p_DATA_RATE_OQ="DDR", p_DATA_RATE_TQ="BUF",
p_TRISTATE_WIDTH=1, p_DATA_WIDTH=8, p_TRISTATE_WIDTH=1,
o_OQ=pad, o_TQ=self.t_out, o_OQ=pad, o_TQ=self.t_out,
i_CLK=ClockSignal("rtiox4"), i_CLK=ClockSignal("rtiox4"),
i_CLKDIV=ClockSignal("rio_phy"), i_CLKDIV=ClockSignal("rio_phy"),