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libboard/sdram: limit write leveling scan to "512 - initial dqs taps delay" on ultrascale

This commit is contained in:
Florent Kermarrec 2018-03-09 19:06:47 +01:00
parent a95cd423cc
commit 5af4609053
1 changed files with 12 additions and 2 deletions
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14
artiq/firmware/libboard/sdram.rs
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@ -39,6 +39,11 @@ mod ddr {
enable_write_leveling(true); enable_write_leveling(true);
spin_cycles(100); spin_cycles(100);
let mut ddrphy_max_delay : u16 = DDRPHY_MAX_DELAY;
#[cfg(kusddrphy)] {
ddrphy_max_delay -= ddrphy::wdly_dqs_taps_read();
}
for n in 0..DQS_SIGNAL_COUNT { for n in 0..DQS_SIGNAL_COUNT {
let dq_addr = dfii::PI0_RDDATA_ADDR let dq_addr = dfii::PI0_RDDATA_ADDR
.offset((DQS_SIGNAL_COUNT - 1 - n) as isize); .offset((DQS_SIGNAL_COUNT - 1 - n) as isize);
@ -55,7 +60,7 @@ mod ddr {
} }
let mut dq; let mut dq;
for _ in 0..DDRPHY_MAX_DELAY { for _ in 0..ddrphy_max_delay {
ddrphy::wlevel_strobe_write(1); ddrphy::wlevel_strobe_write(1);
spin_cycles(10); spin_cycles(10);
dq = ptr::read_volatile(dq_addr); dq = ptr::read_volatile(dq_addr);
@ -87,6 +92,11 @@ mod ddr {
enable_write_leveling(true); enable_write_leveling(true);
spin_cycles(100); spin_cycles(100);
let mut ddrphy_max_delay : u16 = DDRPHY_MAX_DELAY;
#[cfg(kusddrphy)] {
ddrphy_max_delay -= ddrphy::wdly_dqs_taps_read();
}
let mut failed = false; let mut failed = false;
for n in 0..DQS_SIGNAL_COUNT { for n in 0..DQS_SIGNAL_COUNT {
let dq_addr = dfii::PI0_RDDATA_ADDR let dq_addr = dfii::PI0_RDDATA_ADDR
@ -108,7 +118,7 @@ mod ddr {
let mut incr_delay = || { let mut incr_delay = || {
delay[n] += 1; delay[n] += 1;
if delay[n] >= DDRPHY_MAX_DELAY { if delay[n] >= ddrphy_max_delay {
failed = true; failed = true;
return false return false
} }