From 59a3ea4f1596f29be3ca6896725cb4f97147c324 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 18 Dec 2015 15:44:20 +0800
Subject: [PATCH] gateware/rtio/analyzer: fix bus write

---
 artiq/gateware/rtio/analyzer.py | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py
index d83ffa96d..f34be001a 100644
--- a/artiq/gateware/rtio/analyzer.py
+++ b/artiq/gateware/rtio/analyzer.py
@@ -187,11 +187,8 @@ class DMAWriter(Module, AutoCSR):
         )
         fsm.act("WRITE",
             self.busy.status.eq(1),
-
             membus.cyc.eq(1),
             membus.stb.eq(1),
-            membus.we.eq(1),
-            membus.sel.eq(2**len(membus.sel)-1),
 
             If(membus.ack,
                 If(membus.adr == self.last_address.storage,
@@ -204,6 +201,11 @@ class DMAWriter(Module, AutoCSR):
                 NextState("IDLE")
             )
         )
+        self.comb += [
+            membus.we.eq(1),
+            membus.sel.eq(2**len(membus.sel)-1),
+            membus.dat_w.eq(self.sink.data)
+        ]
 
 
 class Analyzer(Module, AutoCSR):