srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

ddb_template: support urukul single-eem mode

This commit is contained in:
Robert Jördens 2019-06-13 12:18:58 +00:00
parent 967d192cbe
commit 591de0e579
1 changed files with 14 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
artiq/frontend/artiq_ddb_template.py
View File

@ -112,7 +112,6 @@ class PeripheralManager:
channel=rtio_offset+next(channel)) channel=rtio_offset+next(channel))
return next(channel) return next(channel)
# TODO: support 1-EEM mode
def process_urukul(self, rtio_offset, peripheral): def process_urukul(self, rtio_offset, peripheral):
urukul_name = self.get_name("urukul") urukul_name = self.get_name("urukul")
synchronization = peripheral.get("synchronization", False) synchronization = peripheral.get("synchronization", False)
@ -153,17 +152,18 @@ class PeripheralManager:
}}""", }}""",
name=urukul_name, name=urukul_name,
channel=rtio_offset+next(channel)) channel=rtio_offset+next(channel))
for i in range(4): if len(peripheral["ports"]) > 1:
self.gen(""" for i in range(4):
device_db["ttl_{name}_sw{uchn}"] = {{ self.gen("""
"type": "local", device_db["ttl_{name}_sw{uchn}"] = {{
"module": "artiq.coredevice.ttl", "type": "local",
"class": "TTLOut", "module": "artiq.coredevice.ttl",
"arguments": {{"channel": 0x{channel:06x}}} "class": "TTLOut",
}}""", "arguments": {{"channel": 0x{channel:06x}}}
name=urukul_name, }}""",
uchn=i, name=urukul_name,
channel=rtio_offset+next(channel)) uchn=i,
channel=rtio_offset+next(channel))
self.gen(""" self.gen("""
device_db["{name}_cpld"] = {{ device_db["{name}_cpld"] = {{
"type": "local", "type": "local",
@ -193,13 +193,13 @@ class PeripheralManager:
"arguments": {{ "arguments": {{
"pll_n": 32, "pll_n": 32,
"chip_select": {chip_select}, "chip_select": {chip_select},
"cpld_device": "{name}_cpld", "cpld_device": "{name}_cpld"{pll_vco}{sync_delay_seed}{io_update_delay}
"sw_device": "ttl_{name}_sw{uchn}"{pll_vco}{sync_delay_seed}{io_update_delay}
}} }}
}}""", }}""",
name=urukul_name, name=urukul_name,
chip_select=4 + i, chip_select=4 + i,
uchn=i, uchn=i,
sw=",\n \"sw_device\": \"ttl_{name}_sw{uchn}\"".format(name=urukul_name, uchn=i) if len(peripheral["ports"]) > 1 else "",
pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "", pll_vco=",\n \"pll_vco\": {}".format(pll_vco) if pll_vco is not None else "",
sync_delay_seed=",\n \"sync_delay_seed\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "", sync_delay_seed=",\n \"sync_delay_seed\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "",
io_update_delay=",\n \"io_update_delay\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "") io_update_delay=",\n \"io_update_delay\": \"eeprom_{}:{}\"".format(urukul_name, 64 + 4*i) if synchronization else "")