forked from M-Labs/artiq
firmware: libboard: extract irq.rs, csr.rs.
This commit is contained in:
whitequark
parent
3c01a1c93f
commit
58a95c1f40
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@ -0,0 +1,25 @@
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use super::spr::*;
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pub fn get_ie() -> bool {
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unsafe { mfspr(SPR_SR) & SPR_SR_IEE != 0 }
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}
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pub fn set_ie(ie: bool) {
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if ie {
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unsafe { mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE) }
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} else {
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unsafe { mtspr(SPR_SR, mfspr(SPR_SR) & !SPR_SR_IEE) }
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}
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}
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pub fn get_mask() -> u32 {
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unsafe { mfspr(SPR_PICMR) }
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}
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pub fn set_mask(mask: u32) {
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unsafe { mtspr(SPR_PICMR, mask) }
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}
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pub fn pending() -> u32 {
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unsafe { mfspr(SPR_PICSR) }
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}
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@ -5,129 +5,8 @@ use core::{cmp, ptr, str};
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/mem.rs"));
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include!(concat!(env!("BUILDINC_DIRECTORY"), "/generated/csr.rs"));
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pub mod spr {
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pub unsafe fn mfspr(reg: u32) -> u32 {
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let value: u32;
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asm!("l.mfspr $0, $1, 0" : "=r"(value) : "r"(reg) : : "volatile");
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value
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}
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pub unsafe fn mtspr(reg: u32, value: u32) {
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asm!("l.mtspr $0, $1, 0" : : "r"(reg), "r"(value) : : "volatile")
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}
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/* Definition of special-purpose registers (SPRs). */
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pub const MAX_GRPS: u32 = 32;
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pub const MAX_SPRS_PER_GRP_BITS: u32 = 11;
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pub const MAX_SPRS_PER_GRP: u32 = 1 << MAX_SPRS_PER_GRP_BITS;
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pub const MAX_SPRS: u32 = 0x10000;
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/* Base addresses for the groups */
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pub const SPRGROUP_SYS: u32 = 0 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_DMMU: u32 = 1 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_IMMU: u32 = 2 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_DC: u32 = 3 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_IC: u32 = 4 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_MAC: u32 = 5 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_D: u32 = 6 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_PC: u32 = 7 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_PM: u32 = 8 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_PIC: u32 = 9 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_TT: u32 = 10 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_FP: u32 = 11 << MAX_SPRS_PER_GRP_BITS;
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/* System control and status group */
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pub const SPR_VR: u32 = SPRGROUP_SYS + 0;
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pub const SPR_UPR: u32 = SPRGROUP_SYS + 1;
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pub const SPR_CPUCFGR: u32 = SPRGROUP_SYS + 2;
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pub const SPR_DMMUCFGR: u32 = SPRGROUP_SYS + 3;
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pub const SPR_IMMUCFGR: u32 = SPRGROUP_SYS + 4;
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pub const SPR_DCCFGR: u32 = SPRGROUP_SYS + 5;
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pub const SPR_ICCFGR: u32 = SPRGROUP_SYS + 6;
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pub const SPR_DCFGR: u32 = SPRGROUP_SYS + 7;
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pub const SPR_PCCFGR: u32 = SPRGROUP_SYS + 8;
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pub const SPR_VR2: u32 = SPRGROUP_SYS + 9;
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pub const SPR_AVR: u32 = SPRGROUP_SYS + 10;
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pub const SPR_EVBAR: u32 = SPRGROUP_SYS + 11;
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pub const SPR_AECR: u32 = SPRGROUP_SYS + 12;
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pub const SPR_AESR: u32 = SPRGROUP_SYS + 13;
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pub const SPR_NPC: u32 = SPRGROUP_SYS + 16; /* CZ 21/06/01 */
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pub const SPR_SR: u32 = SPRGROUP_SYS + 17; /* CZ 21/06/01 */
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pub const SPR_PPC: u32 = SPRGROUP_SYS + 18; /* CZ 21/06/01 */
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pub const SPR_FPCSR: u32 = SPRGROUP_SYS + 20; /* CZ 21/06/01 */
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pub const SPR_ISR_BASE: u32 = SPRGROUP_SYS + 21;
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pub const SPR_EPCR_BASE: u32 = SPRGROUP_SYS + 32; /* CZ 21/06/01 */
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pub const SPR_EPCR_LAST: u32 = SPRGROUP_SYS + 47; /* CZ 21/06/01 */
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pub const SPR_EEAR_BASE: u32 = SPRGROUP_SYS + 48;
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pub const SPR_EEAR_LAST: u32 = SPRGROUP_SYS + 63;
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pub const SPR_ESR_BASE: u32 = SPRGROUP_SYS + 64;
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pub const SPR_ESR_LAST: u32 = SPRGROUP_SYS + 79;
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pub const SPR_GPR_BASE: u32 = SPRGROUP_SYS + 1024;
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// [snip]
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/* PIC group */
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pub const SPR_PICMR: u32 = SPRGROUP_PIC + 0;
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pub const SPR_PICPR: u32 = SPRGROUP_PIC + 1;
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pub const SPR_PICSR: u32 = SPRGROUP_PIC + 2;
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// [snip]
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/*
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* Bit definitions for the Supervision Register
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*
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*/
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pub const SPR_SR_SM: u32 = 0x00000001; /* Supervisor Mode */
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pub const SPR_SR_TEE: u32 = 0x00000002; /* Tick timer Exception Enable */
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pub const SPR_SR_IEE: u32 = 0x00000004; /* Interrupt Exception Enable */
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pub const SPR_SR_DCE: u32 = 0x00000008; /* Data Cache Enable */
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pub const SPR_SR_ICE: u32 = 0x00000010; /* Instruction Cache Enable */
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pub const SPR_SR_DME: u32 = 0x00000020; /* Data MMU Enable */
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pub const SPR_SR_IME: u32 = 0x00000040; /* Instruction MMU Enable */
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pub const SPR_SR_LEE: u32 = 0x00000080; /* Little Endian Enable */
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pub const SPR_SR_CE: u32 = 0x00000100; /* CID Enable */
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pub const SPR_SR_F: u32 = 0x00000200; /* Condition Flag */
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pub const SPR_SR_CY: u32 = 0x00000400; /* Carry flag */
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pub const SPR_SR_OV: u32 = 0x00000800; /* Overflow flag */
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pub const SPR_SR_OVE: u32 = 0x00001000; /* Overflow flag Exception */
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pub const SPR_SR_DSX: u32 = 0x00002000; /* Delay Slot Exception */
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pub const SPR_SR_EPH: u32 = 0x00004000; /* Exception Prefix High */
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pub const SPR_SR_FO: u32 = 0x00008000; /* Fixed one */
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pub const SPR_SR_SUMRA: u32 = 0x00010000; /* Supervisor SPR read access */
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pub const SPR_SR_RES: u32 = 0x0ffe0000; /* Reserved */
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pub const SPR_SR_CID: u32 = 0xf0000000; /* Context ID */
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}
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pub mod irq {
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use super::spr::*;
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pub fn get_ie() -> bool {
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unsafe { mfspr(SPR_SR) & SPR_SR_IEE != 0 }
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}
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pub fn set_ie(ie: bool) {
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if ie {
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unsafe { mtspr(SPR_SR, mfspr(SPR_SR) | SPR_SR_IEE) }
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} else {
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unsafe { mtspr(SPR_SR, mfspr(SPR_SR) & !SPR_SR_IEE) }
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}
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}
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pub fn get_mask() -> u32 {
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unsafe { mfspr(SPR_PICMR) }
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}
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pub fn set_mask(mask: u32) {
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unsafe { mtspr(SPR_PICMR, mask) }
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}
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pub fn pending() -> u32 {
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unsafe { mfspr(SPR_PICSR) }
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}
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}
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pub mod spr;
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pub mod irq;
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extern {
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pub fn flush_cpu_dcache();
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@ -0,0 +1,91 @@
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pub unsafe fn mfspr(reg: u32) -> u32 {
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let value: u32;
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asm!("l.mfspr $0, $1, 0" : "=r"(value) : "r"(reg) : : "volatile");
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value
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}
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pub unsafe fn mtspr(reg: u32, value: u32) {
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asm!("l.mtspr $0, $1, 0" : : "r"(reg), "r"(value) : : "volatile")
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}
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/* Definition of special-purpose registers (SPRs). */
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pub const MAX_GRPS: u32 = 32;
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pub const MAX_SPRS_PER_GRP_BITS: u32 = 11;
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pub const MAX_SPRS_PER_GRP: u32 = 1 << MAX_SPRS_PER_GRP_BITS;
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pub const MAX_SPRS: u32 = 0x10000;
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/* Base addresses for the groups */
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pub const SPRGROUP_SYS: u32 = 0 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_DMMU: u32 = 1 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_IMMU: u32 = 2 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_DC: u32 = 3 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_IC: u32 = 4 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_MAC: u32 = 5 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_D: u32 = 6 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_PC: u32 = 7 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_PM: u32 = 8 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_PIC: u32 = 9 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_TT: u32 = 10 << MAX_SPRS_PER_GRP_BITS;
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pub const SPRGROUP_FP: u32 = 11 << MAX_SPRS_PER_GRP_BITS;
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/* System control and status group */
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pub const SPR_VR: u32 = SPRGROUP_SYS + 0;
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pub const SPR_UPR: u32 = SPRGROUP_SYS + 1;
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pub const SPR_CPUCFGR: u32 = SPRGROUP_SYS + 2;
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pub const SPR_DMMUCFGR: u32 = SPRGROUP_SYS + 3;
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pub const SPR_IMMUCFGR: u32 = SPRGROUP_SYS + 4;
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pub const SPR_DCCFGR: u32 = SPRGROUP_SYS + 5;
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pub const SPR_ICCFGR: u32 = SPRGROUP_SYS + 6;
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pub const SPR_DCFGR: u32 = SPRGROUP_SYS + 7;
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pub const SPR_PCCFGR: u32 = SPRGROUP_SYS + 8;
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pub const SPR_VR2: u32 = SPRGROUP_SYS + 9;
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pub const SPR_AVR: u32 = SPRGROUP_SYS + 10;
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pub const SPR_EVBAR: u32 = SPRGROUP_SYS + 11;
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pub const SPR_AECR: u32 = SPRGROUP_SYS + 12;
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pub const SPR_AESR: u32 = SPRGROUP_SYS + 13;
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pub const SPR_NPC: u32 = SPRGROUP_SYS + 16; /* CZ 21/06/01 */
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pub const SPR_SR: u32 = SPRGROUP_SYS + 17; /* CZ 21/06/01 */
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pub const SPR_PPC: u32 = SPRGROUP_SYS + 18; /* CZ 21/06/01 */
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pub const SPR_FPCSR: u32 = SPRGROUP_SYS + 20; /* CZ 21/06/01 */
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pub const SPR_ISR_BASE: u32 = SPRGROUP_SYS + 21;
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pub const SPR_EPCR_BASE: u32 = SPRGROUP_SYS + 32; /* CZ 21/06/01 */
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pub const SPR_EPCR_LAST: u32 = SPRGROUP_SYS + 47; /* CZ 21/06/01 */
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pub const SPR_EEAR_BASE: u32 = SPRGROUP_SYS + 48;
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pub const SPR_EEAR_LAST: u32 = SPRGROUP_SYS + 63;
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pub const SPR_ESR_BASE: u32 = SPRGROUP_SYS + 64;
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pub const SPR_ESR_LAST: u32 = SPRGROUP_SYS + 79;
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pub const SPR_GPR_BASE: u32 = SPRGROUP_SYS + 1024;
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// [snip]
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/* PIC group */
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pub const SPR_PICMR: u32 = SPRGROUP_PIC + 0;
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pub const SPR_PICPR: u32 = SPRGROUP_PIC + 1;
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pub const SPR_PICSR: u32 = SPRGROUP_PIC + 2;
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// [snip]
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/*
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* Bit definitions for the Supervision Register
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*
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*/
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pub const SPR_SR_SM: u32 = 0x00000001; /* Supervisor Mode */
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pub const SPR_SR_TEE: u32 = 0x00000002; /* Tick timer Exception Enable */
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pub const SPR_SR_IEE: u32 = 0x00000004; /* Interrupt Exception Enable */
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pub const SPR_SR_DCE: u32 = 0x00000008; /* Data Cache Enable */
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pub const SPR_SR_ICE: u32 = 0x00000010; /* Instruction Cache Enable */
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pub const SPR_SR_DME: u32 = 0x00000020; /* Data MMU Enable */
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pub const SPR_SR_IME: u32 = 0x00000040; /* Instruction MMU Enable */
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pub const SPR_SR_LEE: u32 = 0x00000080; /* Little Endian Enable */
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pub const SPR_SR_CE: u32 = 0x00000100; /* CID Enable */
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pub const SPR_SR_F: u32 = 0x00000200; /* Condition Flag */
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pub const SPR_SR_CY: u32 = 0x00000400; /* Carry flag */
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pub const SPR_SR_OV: u32 = 0x00000800; /* Overflow flag */
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pub const SPR_SR_OVE: u32 = 0x00001000; /* Overflow flag Exception */
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pub const SPR_SR_DSX: u32 = 0x00002000; /* Delay Slot Exception */
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pub const SPR_SR_EPH: u32 = 0x00004000; /* Exception Prefix High */
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pub const SPR_SR_FO: u32 = 0x00008000; /* Fixed one */
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pub const SPR_SR_SUMRA: u32 = 0x00010000; /* Supervisor SPR read access */
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pub const SPR_SR_RES: u32 = 0x0ffe0000; /* Reserved */
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pub const SPR_SR_CID: u32 = 0xf0000000; /* Context ID */
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