From 57dd163d37e0cadb9f1515113d73ca7e60942662 Mon Sep 17 00:00:00 2001 From: whitequark Date: Sat, 21 Nov 2015 03:27:06 +0800 Subject: [PATCH] transforms.artiq_ir_generator: fix decomposition of explicit delay_mu(). --- artiq/compiler/transforms/artiq_ir_generator.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/compiler/transforms/artiq_ir_generator.py b/artiq/compiler/transforms/artiq_ir_generator.py index a0349d6eb..376d3a48a 100644 --- a/artiq/compiler/transforms/artiq_ir_generator.py +++ b/artiq/compiler/transforms/artiq_ir_generator.py @@ -1525,7 +1525,7 @@ class ARTIQIRGenerator(algorithm.Visitor): arg = self.visit(node.args[0]) arg_mu_float = self.append(ir.Arith(ast.Div(loc=None), arg, self.ref_period)) arg_mu = self.append(ir.Coerce(arg_mu_float, builtins.TInt(types.TValue(64)))) - self.append(ir.Builtin(typ.name + "_mu", [arg_mu], builtins.TNone())) + return self.append(ir.Builtin(typ.name + "_mu", [arg_mu], builtins.TNone())) else: assert False elif types.is_builtin(typ, "now_mu") or types.is_builtin(typ, "delay_mu") \