forked from M-Labs/artiq
transforms.artiq_ir_generator: fix decomposition of explicit delay_mu().
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@ -1525,7 +1525,7 @@ class ARTIQIRGenerator(algorithm.Visitor):
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arg = self.visit(node.args[0])
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arg_mu_float = self.append(ir.Arith(ast.Div(loc=None), arg, self.ref_period))
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arg_mu = self.append(ir.Coerce(arg_mu_float, builtins.TInt(types.TValue(64))))
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self.append(ir.Builtin(typ.name + "_mu", [arg_mu], builtins.TNone()))
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return self.append(ir.Builtin(typ.name + "_mu", [arg_mu], builtins.TNone()))
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else:
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assert False
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elif types.is_builtin(typ, "now_mu") or types.is_builtin(typ, "delay_mu") \
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