forked from M-Labs/artiq
gateware/rtio: keep counter clock domain transfer active during CSR reset
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@ -11,46 +11,47 @@ from misoc.interconnect.csr import *
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from artiq.gateware.rtio import rtlink
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# note: transfer is in rtio/sys domains and not affected by the reset CSRs
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class _GrayCodeTransfer(Module):
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def __init__(self, width):
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self.i = Signal(width) # in rio domain
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self.o = Signal(width) # in rsys domain
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self.i = Signal(width) # in rtio domain
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self.o = Signal(width) # in sys domain
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# # #
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# convert to Gray code
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value_gray_rio = Signal(width)
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self.sync.rio += value_gray_rio.eq(self.i ^ self.i[1:])
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value_gray_rtio = Signal(width)
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self.sync.rtio += value_gray_rtio.eq(self.i ^ self.i[1:])
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# transfer to system clock domain
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value_gray_sys = Signal(width)
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self.specials += [
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NoRetiming(value_gray_rio),
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MultiReg(value_gray_rio, value_gray_sys, "rsys")
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NoRetiming(value_gray_rtio),
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MultiReg(value_gray_rtio, value_gray_sys)
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]
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# convert back to binary
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value_sys = Signal(width)
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self.comb += value_sys[-1].eq(value_gray_sys[-1])
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for i in reversed(range(width-1)):
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self.comb += value_sys[i].eq(value_sys[i+1] ^ value_gray_sys[i])
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self.sync.rsys += self.o.eq(value_sys)
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self.sync += self.o.eq(value_sys)
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class _RTIOCounter(Module):
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def __init__(self, width):
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self.width = width
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# Timestamp counter in RTIO domain
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self.value_rio = Signal(width)
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self.value_rtio = Signal(width)
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# Timestamp counter resynchronized to sys domain
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# Lags behind value_rio, monotonic and glitch-free
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# Lags behind value_rtio, monotonic and glitch-free
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self.value_sys = Signal(width)
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# # #
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# note: counter is in rtio domain and never affected by the reset CSRs
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self.sync.rtio += self.value_rio.eq(self.value_rio + 1)
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self.sync.rtio += self.value_rtio.eq(self.value_rtio + 1)
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gt = _GrayCodeTransfer(width)
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self.submodules += gt
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self.comb += gt.i.eq(self.value_rio), self.value_sys.eq(gt.o)
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self.comb += gt.i.eq(self.value_rtio), self.value_sys.eq(gt.o)
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# CHOOSING A GUARD TIME
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@ -215,7 +216,7 @@ class _OutputManager(Module):
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# TODO: report error on stb & busy
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self.comb += [
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dout_ack.eq(
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dout.timestamp[fine_ts_width:] == counter.value_rio),
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dout.timestamp[fine_ts_width:] == counter.value_rtio),
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interface.stb.eq(dout_stb & dout_ack)
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]
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if data_width:
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@ -260,9 +261,9 @@ class _InputManager(Module):
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self.comb += fifo_in.data.eq(interface.data)
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if interface.timestamped:
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if fine_ts_width:
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full_ts = Cat(interface.fine_ts, counter.value_rio)
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full_ts = Cat(interface.fine_ts, counter.value_rtio)
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else:
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full_ts = counter.value_rio
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full_ts = counter.value_rtio
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self.comb += fifo_in.timestamp.eq(full_ts)
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self.comb += fifo.we.eq(interface.stb)
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