diff --git a/artiq/gateware/rtio/xilinx_clocking.py b/artiq/gateware/rtio/xilinx_clocking.py
index 20e0c36c6..aff4786bf 100644
--- a/artiq/gateware/rtio/xilinx_clocking.py
+++ b/artiq/gateware/rtio/xilinx_clocking.py
@@ -1,39 +1,3 @@
-from migen import *
-from migen.genlib.cdc import MultiReg
-from misoc.interconnect.csr import *
-
-
-class RTIOClockMultiplier(Module, AutoCSR):
-    def __init__(self, rtio_clk_freq):
-        self.pll_reset = CSRStorage(reset=1)
-        self.pll_locked = CSRStatus()
-        self.clock_domains.cd_rtiox4 = ClockDomain(reset_less=True)
-
-        # See "Global Clock Network Deskew Using Two BUFGs" in ug472.
-        clkfbout = Signal()
-        clkfbin = Signal()
-        rtiox4_clk = Signal()
-        pll_locked = Signal()
-        self.specials += [
-            Instance("MMCME2_BASE",
-                     p_CLKIN1_PERIOD=1e9/rtio_clk_freq,
-                     i_CLKIN1=ClockSignal("sys"),
-                     i_RST=self.pll_reset.storage,
-                     o_LOCKED=pll_locked,
-
-                     p_CLKFBOUT_MULT_F=8.0, p_DIVCLK_DIVIDE=1,
-
-                     o_CLKFBOUT=clkfbout, i_CLKFBIN=clkfbin,
-
-                     p_CLKOUT0_DIVIDE_F=2.0, o_CLKOUT0=rtiox4_clk,
-                     ),
-            Instance("BUFG", i_I=clkfbout, o_O=clkfbin),
-            Instance("BUFG", i_I=rtiox4_clk, o_O=self.cd_rtiox4.clk),
-
-            MultiReg(pll_locked, self.pll_locked.status)
-        ]
-
-
 def fix_serdes_timing_path(platform):
     # ignore timing of path from OSERDESE2 through the pad to ISERDESE2
     platform.add_platform_command(
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 3ad5f5bdf..037b9f108 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -17,7 +17,7 @@ from misoc.integration.builder import builder_args, builder_argdict
 from artiq.gateware.amp import AMPSoC
 from artiq.gateware import rtio, nist_clock, nist_qc2
 from artiq.gateware.rtio.phy import ttl_simple, ttl_serdes_7series, dds, spi2
-from artiq.gateware.rtio.xilinx_clocking import RTIOClockMultiplier, fix_serdes_timing_path
+from artiq.gateware.rtio.xilinx_clocking import fix_serdes_timing_path
 from artiq.gateware.drtio.transceiver import gtx_7series
 from artiq.gateware.drtio.siphaser import SiPhaser7Series
 from artiq.gateware.drtio.rx_synchronizer import XilinxRXSynchronizer