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metlino: drive clock muxes

This commit is contained in:
Sebastien Bourdeauducq 2020-02-05 00:06:34 +08:00
parent a2d2ec9238
commit 5733d70041
1 changed files with 2 additions and 0 deletions
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2
artiq/gateware/targets/metlino.py
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@ -53,6 +53,8 @@ class Master(MiniSoC, AMPSoC):
platform = self.platform
rtio_clk_freq = 150e6
self.comb += platform.request("input_clk_sel").eq(1)
self.comb += platform.request("filtered_clk_sel").eq(1)
self.submodules.si5324_rst_n = gpio.GPIOOut(platform.request("si5324").rst_n)
self.csr_devices.append("si5324_rst_n")
i2c = self.platform.request("i2c")