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sayma_rtm_drtio: add HMC clock chip and DAC control

This commit is contained in:
Sebastien Bourdeauducq 2019-10-06 16:15:24 +08:00
parent a8cf4c2b18
commit 5612b31860
1 changed files with 26 additions and 0 deletions
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26
artiq/gateware/targets/sayma_rtm_drtio.py
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@ -10,6 +10,7 @@ from migen.genlib.cdc import MultiReg
from misoc.interconnect.csr import * from misoc.interconnect.csr import *
from misoc.cores import gpio from misoc.cores import gpio
from misoc.cores import spi2
from misoc.cores.a7_gtp import * from misoc.cores.a7_gtp import *
from misoc.targets.sayma_rtm import BaseSoC, soc_sayma_rtm_args, soc_sayma_rtm_argdict from misoc.targets.sayma_rtm import BaseSoC, soc_sayma_rtm_args, soc_sayma_rtm_argdict
from misoc.integration.builder import Builder, builder_args, builder_argdict from misoc.integration.builder import Builder, builder_args, builder_argdict
@ -165,6 +166,31 @@ class _SatelliteBase(BaseSoC):
self.csr_devices.append("rtio_crg") self.csr_devices.append("rtio_crg")
fix_serdes_timing_path(platform) fix_serdes_timing_path(platform)
# HMC clock chip and DAC control
self.comb += platform.request("ad9154_rst_n", 0).eq(1)
if self.hw_rev == "v2.0":
self.comb += platform.request("ad9154_rst_n", 1).eq(1)
self.submodules.converter_spi = spi2.SPIMaster(spi2.SPIInterface(
platform.request("hmc_spi"),
platform.request("ad9154_spi", 0),
platform.request("ad9154_spi", 1)))
self.csr_devices.append("converter_spi")
self.submodules.hmc7043_reset = gpio.GPIOOut(
platform.request("hmc7043_reset"), reset_out=1)
self.csr_devices.append("hmc7043_reset")
self.submodules.hmc7043_gpo = gpio.GPIOIn(
platform.request("hmc7043_gpo"))
self.csr_devices.append("hmc7043_gpo")
if self.hw_rev == "v2.0":
self.comb += platform.request("hmc830_pwr_en").eq(1)
self.submodules.hmc7043_out_en = gpio.GPIOOut(
platform.request("hmc7043_out_en"))
self.csr_devices.append("hmc7043_out_en")
self.config["HAS_HMC830_7043"] = None
self.config["CONVERTER_SPI_HMC830_CS"] = 0
self.config["CONVERTER_SPI_HMC7043_CS"] = 1
self.config["HMC830_REF"] = "150"
def add_rtio(self, rtio_channels): def add_rtio(self, rtio_channels):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")