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phaser: use ttl_simple.Input for sync

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Robert Jördens 2016-11-24 15:55:26 +01:00
parent 6fa2a6ebd8
commit 55e37b41ec
1 changed files with 1 additions and 1 deletions
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artiq/gateware/targets/phaser.py
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@ -206,7 +206,7 @@ class Phaser(MiniSoC, AMPSoC):
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
ofifo_depth=2))
phy = ttl_serdes_7series.Inout_8X(self.ad9154.jesd.jsync)
phy = ttl_simple.Input(self.ad9154.jesd.jsync)
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=32,
ofifo_depth=2))