forked from M-Labs/artiq
sayma_rtm: use CSR infrastructure, generate CSR CSV
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54c75d3274
@ -1,10 +1,15 @@
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#!/usr/bin/env python3
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import os
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.build.platforms.sinara import sayma_rtm
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from misoc.interconnect import wishbone, stream
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from misoc.interconnect.csr import *
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from misoc.integration.wb_slaves import WishboneSlaveManager
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from misoc.integration.cpu_interface import get_csr_csv
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from artiq.gateware import serwb
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@ -53,15 +58,27 @@ class CRG(Module):
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self.specials += Instance("IDELAYCTRL", i_REFCLK=ClockSignal("clk200"), i_RST=ic_reset)
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class RTMIdentifier(Module, AutoCSR):
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def __init__(self):
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self.identifier = CSRStatus(32)
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self.comb += self.identifier.status.eq(0x5352544d) # "SRTM"
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CSR_RANGE_SIZE = 0x800
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class SaymaRTM(Module):
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def __init__(self, platform):
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csr_devices = []
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self.submodules.crg = CRG(platform)
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self.crg.cd_sys.clk.attr.add("keep")
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clk_freq = 125e6
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platform.add_period_constraint(self.crg.cd_sys.clk, 8.0)
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sram = wishbone.SRAM(8192, init=[0x12345678, 0xbadc0f33, 0xabad1dea, 0xdeadbeef])
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self.submodules += sram
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self.submodules.rtm_identifier = RTMIdentifier()
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csr_devices.append("rtm_identifier")
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# TODO: push all those serwb bits into library modules
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# maybe keep only 3 user-visible modules: serwb PLL, serwb PHY, and serwb core
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@ -120,14 +137,32 @@ class SaymaRTM(Module):
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serwb_rx_cdc.source.connect(serwb_depacketizer.sink),
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]
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# connect serwb to SRAM
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self.comb += serwb_etherbone.wishbone.bus.connect(sram.bus)
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# process CSR devices and connect them to serwb
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self.csr_regions = []
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wb_slaves = WishboneSlaveManager(0x10000000)
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for i, name in enumerate(csr_devices):
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origin = i*CSR_RANGE_SIZE
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module = getattr(self, name)
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csrs = module.get_csrs()
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bank = wishbone.CSRBank(csrs)
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self.submodules += bank
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wb_slaves.add(origin, CSR_RANGE_SIZE, bank.bus)
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self.csr_regions.append((name, origin, 32, csrs))
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self.submodules += wishbone.Decoder(serwb_etherbone.wishbone.bus,
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wb_slaves.get_interconnect_slaves(),
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register=True)
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def main():
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build_dir = "artiq_sayma_rtm"
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platform = sayma_rtm.Platform()
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top = SaymaRTM(platform)
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platform.build(top, build_dir="artiq_sayma_rtm")
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with open(os.path.join(build_dir, "sayma_rtm_csr.csv"), "w") as f:
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f.write(get_csr_csv(top.csr_regions))
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platform.build(top, build_dir=build_dir)
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if __name__ == "__main__":
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