forked from M-Labs/artiq
artiq_flash: flash RTM firmware
based on whitequark's work in f95fb27
m-labs/artiq#813
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0c49201be7
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54984f080b
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@ -256,28 +256,29 @@ def main():
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config = {
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"kc705": {
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"programmer": partial(ProgrammerXC7, board="kc705", proxy="bscan_spi_xc7k325t.bit"),
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"variants": ["nist_clock", "nist_qc2"],
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi0", 0xaf0000),
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"storage": ("spi0", 0xb30000),
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"firmware": ("spi0", 0xb40000),
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"programmer": partial(ProgrammerXC7, board="kc705", proxy="bscan_spi_xc7k325t.bit"),
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"variants": ["nist_clock", "nist_qc2"],
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi0", 0xaf0000),
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"storage": ("spi0", 0xb30000),
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"firmware": ("spi0", 0xb40000),
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},
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"kasli": {
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"programmer": partial(ProgrammerXC7, board="kasli", proxy="bscan_spi_xc7a100t.bit"),
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"variants": ["opticlock", "master", "satellite"],
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi0", 0x400000),
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"storage": ("spi0", 0x440000),
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"firmware": ("spi0", 0x450000),
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"programmer": partial(ProgrammerXC7, board="kasli", proxy="bscan_spi_xc7a100t.bit"),
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"variants": ["opticlock", "master", "satellite"],
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi0", 0x400000),
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"storage": ("spi0", 0x440000),
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"firmware": ("spi0", 0x450000),
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},
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"sayma": {
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"programmer": ProgrammerSayma,
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"variants": ["standalone", "master", "satellite"],
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi1", 0x000000),
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"storage": ("spi1", 0x040000),
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"firmware": ("spi1", 0x050000),
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"programmer": ProgrammerSayma,
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"variants": ["standalone", "master", "satellite"],
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"gateware": ("spi0", 0x000000),
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"bootloader": ("spi1", 0x000000),
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"storage": ("spi1", 0x040000),
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"firmware": ("spi1", 0x050000),
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"rtm_gateware": ("spi1", 0x150000),
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},
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}[args.target]
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@ -309,18 +310,34 @@ def main():
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else:
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return os.path.join(args.srcbuild, *path_filename)
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def convert_gateware(bit_filename, header=False):
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bin_handle, bin_filename = tempfile.mkstemp(
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prefix="artiq_", suffix="_" + os.path.basename(bit_filename))
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with open(bit_filename, "rb") as bit_file, \
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open(bin_handle, "wb") as bin_file:
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if header:
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bin_file.write(b"\x00"*8)
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bit2bin(bit_file, bin_file)
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if header:
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magic = 0x53415231 # "SAR1"
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length = bin_file.tell() - 8
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bin_file.seek(0)
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bin_file.write(magic.to_bytes(4, byteorder="big"))
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bin_file.write(length.to_bytes(4, byteorder="big"))
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atexit.register(lambda: os.unlink(bin_filename))
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return bin_filename
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try:
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for action in args.action:
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if action == "gateware":
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gateware_bin = artifact_path(variant, "gateware", "top.bin")
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if not os.access(gateware_bin, os.R_OK):
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bin_handle, gateware_bin = tempfile.mkstemp()
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gateware_bit = artifact_path(variant, "gateware", "top.bit")
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with open(gateware_bit, "rb") as bit_file, open(bin_handle, "wb") as bin_file:
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bit2bin(bit_file, bin_file)
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atexit.register(lambda: os.unlink(gateware_bin))
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gateware_bin = convert_gateware(
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artifact_path(variant, "gateware", "top.bit"))
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programmer.write_binary(*config["gateware"], gateware_bin)
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if args.target == "sayma":
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rtm_gateware_bin = convert_gateware(
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artifact_path("rtm_gateware", "rtm.bit"), header=True)
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programmer.write_binary(*config["rtm_gateware"],
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rtm_gateware_bin)
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elif action == "bootloader":
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bootloader_bin = artifact_path(variant, "software", "bootloader", "bootloader.bin")
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programmer.write_binary(*config["bootloader"], bootloader_bin)
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@ -171,7 +171,7 @@ class Standalone(MiniSoC, AMPSoC):
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])
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self.csr_devices.append("slave_fpga_cfg")
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self.config["HAS_SLAVE_FPGA"] = None
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self.config["SLAVE_FPGA_GATEWARE"] = 0xde0000
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self.config["SLAVE_FPGA_GATEWARE"] = 0x150000
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# AMC/RTM serwb
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serwb_pll = serwb.phy.SERWBPLL(125e6, 625e6, vco_div=2)
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