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gateware.spi: rewrite counter bias for timing

This commit is contained in:
Robert Jördens 2016-02-29 02:28:19 +01:00
parent 9a1d6a51a4
commit 5480099f1b
1 changed files with 11 additions and 4 deletions
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15
artiq/gateware/spi.py
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@ -13,14 +13,21 @@ class SPIClockGen(Module):
self.clk = Signal(reset=1) self.clk = Signal(reset=1)
cnt = Signal.like(self.load) cnt = Signal.like(self.load)
bias = Signal()
zero = Signal()
self.comb += [ self.comb += [
self.edge.eq(cnt == 0), zero.eq(cnt == 0),
self.edge.eq(zero & ~bias),
] ]
self.sync += [ self.sync += [
cnt.eq(cnt - 1), If(zero,
bias.eq(0),
).Else(
cnt.eq(cnt - 1),
),
If(self.edge, If(self.edge,
cnt.eq(self.load[1:] + cnt.eq(self.load[1:]),
(self.load[0] & (self.clk ^ self.bias))), bias.eq(self.load[0] & (self.clk ^ self.bias)),
self.clk.eq(~self.clk), self.clk.eq(~self.clk),
) )
] ]