From 53facfef133d841661cdb163e000e8ff23ecbe4c Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 22 Jan 2018 18:33:22 +0800 Subject: [PATCH] sayma: build fixes --- artiq/gateware/targets/sayma_amc.py | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 27692219a..f7a22873d 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -9,12 +9,15 @@ from migen import * from migen.genlib.resetsync import AsyncResetSynchronizer from migen.genlib.io import DifferentialInput +from microscope import * + +from misoc.cores import gpio from misoc.cores.slave_fpga import SlaveFPGA from misoc.integration.soc_sdram import soc_sdram_args, soc_sdram_argdict from misoc.integration.builder import builder_args, builder_argdict from misoc.interconnect import stream from misoc.interconnect.csr import * -from misoc.targets.sayma_amc import MiniSoC +from misoc.targets.sayma_amc import BaseSoC, MiniSoC from jesd204b.common import (JESD204BTransportSettings, JESD204BPhysicalSettings, @@ -262,7 +265,7 @@ class Master(MiniSoC, AMPSoC): } mem_map.update(MiniSoC.mem_map) - def __init__(self, **kwargs): + def __init__(self, with_sawg, **kwargs): MiniSoC.__init__(self, cpu_type="or1k", sdram_controller_type="minicon", @@ -273,6 +276,9 @@ class Master(MiniSoC, AMPSoC): **kwargs) AMPSoC.__init__(self) + if with_sawg: + warnings.warn("SAWG is not implemented yet with DRTIO, ignoring.") + platform = self.platform rtio_clk_freq = 150e6