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devices/dds_core: use MPO and runtime IF

This commit is contained in:
Sebastien Bourdeauducq 2014-07-23 11:50:23 -06:00
parent ba088614d8
commit 52e8d4150b
1 changed files with 7 additions and 11 deletions

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@ -1,25 +1,21 @@
from artiq.language.core import * from artiq.language.core import *
from artiq.language.units import * from artiq.language.units import *
class DDS: class DDS(MPO):
def __init__(self, core, reg_channel, rtio_channel, latency=0*ps, phase_mode="continuous"): parameters = "dds_sysclk reg_channel rtio_channel"
self.core = core
self.reg_channel = reg_channel
self.rtio_channel = rtio_channel
self.latency = latency
self.phase_mode = phase_mode
def build(self):
self._previous_frequency = 0*MHz self._previous_frequency = 0*MHz
kernel_attr_ro = "reg_channel rtio_channel latency phase_mode"
kernel_attr = "_previous_frequency" kernel_attr = "_previous_frequency"
@kernel @kernel
def pulse(self, frequency, duration): def pulse(self, frequency, duration):
if self._previous_frequency != frequency: if self._previous_frequency != frequency:
syscall("rtio_sync", self.rtio_channel) # wait until output is off syscall("rtio_sync", self.rtio_channel) # wait until output is off
syscall("dds_program", self.reg_channel, frequency) syscall("dds_program", self.reg_channel,
(frequency << 2)//(self.dds_sysclk >> 15) << 15)
self._previous_frequency = frequency self._previous_frequency = frequency
syscall("rtio_set", now()-self.latency, self.rtio_channel, 1) syscall("rtio_set", now(), self.rtio_channel, 1)
delay(duration) delay(duration)
syscall("rtio_set", now()-self.latency, self.rtio_channel, 0) syscall("rtio_set", now(), self.rtio_channel, 0)