forked from M-Labs/artiq
urukul: rework EEPROM synchronization. Closes #1372
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bc3b55b1a8
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5279bc275a
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@ -1,5 +1,4 @@
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from numpy import int32, int64
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import functools
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from artiq.language.core import (
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kernel, delay, portable, delay_mu, now_mu, at_mu)
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@ -62,6 +61,43 @@ RAM_MODE_CONT_BIDIR_RAMP = 3
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RAM_MODE_CONT_RAMPUP = 4
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class SyncDataUser:
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def __init__(self, core, sync_delay_seed, io_update_delay):
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self.core = core
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self.sync_delay_seed = sync_delay_seed
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self.io_update_delay = io_update_delay
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@kernel
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def init(self):
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pass
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class SyncDataEeprom:
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def __init__(self, dmgr, core, eeprom_str):
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self.core = core
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eeprom_device, eeprom_offset = eeprom_str.split(":")
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self.eeprom_device = dmgr.get(eeprom_device)
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self.eeprom_offset = int(eeprom_offset)
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self.sync_delay_seed = 0
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self.io_update_delay = 0
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@kernel
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def init(self):
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word = self.eeprom_device.read_i32(self.eeprom_offset) >> 16
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sync_delay_seed = word >> 8
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if sync_delay_seed >= 0:
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io_update_delay = word & 0xff
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else:
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io_update_delay = 0
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if io_update_delay == 0xff: # unprogrammed EEPROM
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io_update_delay = 0
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# With Numpy, type(int32(-1) >> 1) == int64
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self.sync_delay_seed = int32(sync_delay_seed)
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self.io_update_delay = int32(io_update_delay)
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class AD9910:
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"""
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AD9910 DDS channel on Urukul.
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@ -88,15 +124,17 @@ class AD9910:
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and set this to the delay tap number returned (default: -1 to signal no
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synchronization and no tuning during :meth:`init`).
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Can be a string of the form "eeprom_device:byte_offset" to read the value
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from a I2C EEPROM.
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from a I2C EEPROM; in which case, `io_update_delay` must be set to the
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same string value.
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:param io_update_delay: IO_UPDATE pulse alignment delay.
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To align IO_UPDATE to SYNC_CLK, run :meth:`tune_io_update_delay` and
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set this to the delay tap number returned.
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Can be a string of the form "eeprom_device:byte_offset" to read the value
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from a I2C EEPROM.
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from a I2C EEPROM; in which case, `sync_delay_seed` must be set to the
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same string value.
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"""
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kernel_invariants = {"chip_select", "cpld", "core", "bus",
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"ftw_per_hz", "io_update_delay", "sysclk_per_mu"}
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"ftw_per_hz", "sysclk_per_mu"}
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def __init__(self, dmgr, chip_select, cpld_device, sw_device=None,
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pll_n=40, pll_cp=7, pll_vco=5, sync_delay_seed=-1,
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@ -128,41 +166,14 @@ class AD9910:
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assert sysclk <= 1e9
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self.ftw_per_hz = (1 << 32)/sysclk
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self.sysclk_per_mu = int(round(sysclk*self.core.ref_period))
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self.sysclk = sysclk
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@functools.lru_cache(maxsize=2)
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def get_eeprom_sync_data(eeprom_str):
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device, offset = eeprom_str.split(":")
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device = dmgr.get(device)
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offset = int(offset)
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word = device.read_i32(offset) >> 16
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sync_delay_seed = word >> 8
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if sync_delay_seed >= 0:
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io_update_delay = word & 0xff
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if isinstance(sync_delay_seed, str) or isinstance(io_update_delay, str):
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if sync_delay_seed != io_update_delay:
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raise ValueError("When using EEPROM, sync_delay_seed must be equal to io_update_delay")
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self.sync_data = SyncDataEeprom(dmgr, self.core, sync_delay_seed)
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else:
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io_update_delay = 0
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if io_update_delay == 0xff: # unprogrammed EEPROM
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io_update_delay = 0
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# With Numpy, type(int32(-1) >> 1) == int64
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return device, offset, int32(sync_delay_seed), int32(io_update_delay)
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if isinstance(sync_delay_seed, str):
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self.sync_delay_seed_eeprom, self.sync_delay_seed_offset, sync_delay_seed, _ = \
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get_eeprom_sync_data(sync_delay_seed)
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else:
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self.sync_delay_seed_eeprom, self.sync_delay_seed_offset = None, None
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if isinstance(io_update_delay, str):
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self.io_update_delay_eeprom, self.io_update_delay_offset, _, io_update_delay = \
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get_eeprom_sync_data(io_update_delay)
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else:
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self.io_update_delay_eeprom, self.io_update_delay_offset = None, None
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if sync_delay_seed >= 0 and not self.cpld.sync_div:
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raise ValueError("parent cpld does not drive SYNC")
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self.sync_delay_seed = sync_delay_seed
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if self.sync_delay_seed >= 0:
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assert self.sysclk_per_mu == sysclk*self.core.ref_period
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self.io_update_delay = io_update_delay
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self.sync_data = SyncDataUser(self.core, sync_delay_seed, io_update_delay)
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self.phase_mode = PHASE_MODE_CONTINUOUS
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@ -369,6 +380,14 @@ class AD9910:
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:param blind: Do not read back DDS identity and do not wait for lock.
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"""
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self.sync_data.init()
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if self.sync_data.sync_delay_seed >= 0 and not self.cpld.sync_div:
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raise ValueError("parent cpld does not drive SYNC")
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if self.sync_data.sync_delay_seed >= 0:
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if self.sysclk_per_mu != self.sysclk*self.core.ref_period:
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raise ValueError("incorrect clock ratio for synchronization")
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delay(50*ms) # slack
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# Set SPI mode
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self.set_cfr1()
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self.cpld.io_update.pulse(1*us)
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@ -406,8 +425,8 @@ class AD9910:
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if i >= 100 - 1:
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raise ValueError("PLL lock timeout")
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delay(10*us) # slack
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if self.sync_delay_seed >= 0:
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self.tune_sync_delay(self.sync_delay_seed)
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if self.sync_data.sync_delay_seed >= 0:
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self.tune_sync_delay(self.sync_data.sync_delay_seed)
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delay(1*ms)
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@kernel
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@ -468,7 +487,7 @@ class AD9910:
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pow_ += dt*ftw*self.sysclk_per_mu >> 16
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self.write64(_AD9910_REG_PROFILE0 + profile,
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(asf << 16) | (pow_ & 0xffff), ftw)
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delay_mu(int64(self.io_update_delay))
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delay_mu(int64(self.sync_data.io_update_delay))
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self.cpld.io_update.pulse_mu(8) # assumes 8 mu > t_SYN_CCLK
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at_mu(now_mu() & ~7) # clear fine TSC again
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if phase_mode != PHASE_MODE_CONTINUOUS:
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@ -3,7 +3,7 @@ import os
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import select
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from artiq.experiment import *
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from artiq.coredevice.ad9910 import AD9910
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from artiq.coredevice.ad9910 import AD9910, SyncDataEeprom
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if os.name == "nt":
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import msvcrt
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@ -240,15 +240,11 @@ class KasliTester(EnvExperiment):
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print("Calibrating inter-device synchronization...")
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for channel_name, channel_dev in self.urukuls:
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if (not isinstance(channel_dev, AD9910) or
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(channel_dev.sync_delay_seed_eeprom is None and channel_dev.io_update_delay_eeprom is None)):
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print("{}\tno synchronization".format(channel_name))
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elif channel_dev.sync_delay_seed_eeprom is not channel_dev.io_update_delay_eeprom:
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print("{}\tunsupported EEPROM configuration".format(channel_name))
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elif channel_dev.sync_delay_seed_offset != channel_dev.io_update_delay_offset:
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print("{}\tunsupported EEPROM offsets".format(channel_name))
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not isinstance(channel_dev.sync_data, SyncDataEeprom)):
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print("{}\tno EEPROM synchronization".format(channel_name))
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else:
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eeprom = channel_dev.sync_delay_seed_eeprom
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offset = channel_dev.sync_delay_seed_offset
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eeprom = channel_dev.sync_data.eeprom_device
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offset = channel_dev.sync_data.eeprom_offset
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sync_delay_seed, io_update_delay = self.calibrate_urukul(channel_dev)
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print("{}\t{} {}".format(channel_name, sync_delay_seed, io_update_delay))
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eeprom_word = (sync_delay_seed << 24) | (io_update_delay << 16)
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