forked from M-Labs/artiq
1
0
Fork 0

drtio: add Xilinx RX synchronizer

This commit is contained in:
Sebastien Bourdeauducq 2018-02-19 17:49:43 +08:00
parent 3bc575bee7
commit 52049cf36a
1 changed files with 38 additions and 0 deletions

View File

@ -0,0 +1,38 @@
from migen import *
class XilinxRXSynchronizer(Module):
"""Deterministic RX synchronizer using a relatively placed macro
to put the clock-domain-crossing FFs right next to each other.
To meet setup/hold constraints receiving FFs, adjust the phase shift
of the Si5324.
We assume that FPGA routing variations are small enough to be negligible.
"""
def __init__(self):
self.signals = []
def resync(self, signal):
synchronized = Signal.like(signal, related=signal)
self.signals.append((signal, synchronized))
return synchronized
def do_finalize(self):
l = sum(len(s[0]) for s in self.signals)
din = Signal(l)
inter = Signal(l)
dout = Signal(l)
self.comb += [
din.eq(Cat(*[s[0] for s in self.signals])),
Cat(*[s[1] for s in self.signals]).eq(dout)
]
for i in range(l):
hu_set = ("HU_SET", "drtio_rx_synchronizer")
self.specials += [
Instance("FD", i_C=ClockSignal("rtio_rx"), i_D=din[i], o_Q=inter[i],
attr={hu_set, ("RLOC", "X0Y{}".format(i))}),
Instance("FD", i_C=ClockSignal("rtio"), i_D=inter[i], o_Q=dout[i],
attr={hu_set, ("RLOC", "X1Y{}".format(i))})
]