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remove obsolete SI5324_AS_SYNTHESIZER config option

This commit is contained in:
Sebastien Bourdeauducq 2023-01-12 13:01:08 +08:00
parent 0a37a1a4c1
commit 514ac953ce
4 changed files with 5 additions and 13 deletions
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12
artiq/firmware/runtime/rtio_clocking.rs
View File

@ -1,5 +1,4 @@
use board_misoc::config;
#[cfg(si5324_as_synthesizer)]
use board_artiq::si5324;
use board_misoc::{csr, clock};
@ -86,15 +85,14 @@ pub mod crg {
// Si5324 input to select for locking to an external clock (as opposed to
// a recovered link clock in DRTIO satellites, which is handled elsewhere).
#[cfg(all(si5324_as_synthesizer, soc_platform = "kasli", hw_rev = "v2.0"))]
#[cfg(all(soc_platform = "kasli", hw_rev = "v2.0"))]
const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin1;
#[cfg(all(si5324_as_synthesizer, soc_platform = "kasli", not(hw_rev = "v2.0")))]
#[cfg(all(soc_platform = "kasli", not(hw_rev = "v2.0")))]
const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin2;
#[cfg(all(si5324_as_synthesizer, soc_platform = "kc705"))]
#[cfg(all(soc_platform = "kc705"))]
const SI5324_EXT_INPUT: si5324::Input = si5324::Input::Ckin2;
#[cfg(si5324_as_synthesizer)]
fn setup_si5324_as_synthesizer(cfg: RtioClock) {
fn setup_si5324_pll(cfg: RtioClock) {
let (si5324_settings, si5324_ref_input) = match cfg {
RtioClock::Ext0_Synth0_10to125 => { // 125 MHz output from 10 MHz CLKINx reference, 504 Hz BW
info!("using 10MHz reference to make 125MHz RTIO clock with PLL");
@ -209,7 +207,7 @@ fn setup_si5324(clock_cfg: RtioClock) {
info!("using external RTIO clock with PLL bypass");
si5324::bypass(SI5324_EXT_INPUT).expect("cannot bypass Si5324")
},
_ => setup_si5324_as_synthesizer(clock_cfg),
_ => setup_si5324_pll(clock_cfg),
}
// switch sysclk source to si5324

3
artiq/gateware/targets/kasli.py
View File

@ -136,7 +136,6 @@ class Tester(StandaloneBase):
dds = "ad9910"
StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
# self.config["SI5324_EXT_REF"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
if hw_rev == "v1.0":
@ -174,7 +173,6 @@ class SUServo(StandaloneBase):
hw_rev = "v2.0"
StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
# self.config["SI5324_EXT_REF"] = None
self.config["RTIO_FREQUENCY"] = "125.0"
if hw_rev == "v1.0":
@ -254,7 +252,6 @@ class MasterBase(MiniSoC, AMPSoC):
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_SOFT_RESET"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
drtio_data_pads = []

1
artiq/gateware/targets/kasli_generic.py
View File

@ -23,7 +23,6 @@ class GenericStandalone(StandaloneBase):
self.class_name_override = description["variant"]
StandaloneBase.__init__(self, hw_rev=hw_rev, **kwargs)
self.config["SI5324_AS_SYNTHESIZER"] = None
self.config["RTIO_FREQUENCY"] = "{:.1f}".format(description["rtio_frequency"]/1e6)
if "ext_ref_frequency" in description:
self.config["SI5324_EXT_REF"] = None

2
artiq/gateware/targets/kc705.py
View File

@ -112,7 +112,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
cdr_clk_buf = Signal()
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
self.submodules.si5324_rst_n = gpio.GPIOOut(self.platform.request("si5324_33").rst_n)
self.csr_devices.append("si5324_rst_n")
self.specials += [
@ -262,7 +261,6 @@ class _MasterBase(MiniSoC, AMPSoC):
self.csr_devices.append("i2c")
self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None
self.config["SI5324_AS_SYNTHESIZER"] = None
rtio_clk_period = 1e9/self.drtio_transceiver.rtio_clk_freq
# Constrain TX & RX timing for the first transceiver channel