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coredevice: add some kernel_constant_attributes specifications.

This commit is contained in:
whitequark 2016-03-28 00:05:29 +00:00
parent ca7463a054
commit 507ad96db3
2 changed files with 16 additions and 0 deletions
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6
artiq/coredevice/core.py
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@ -58,6 +58,12 @@ class Core:
factor). factor).
:param comm_device: name of the device used for communications. :param comm_device: name of the device used for communications.
""" """
kernel_constant_attributes = {
'core', 'ref_period', 'coarse_ref_period', 'ref_multiplier',
'external_clock',
}
def __init__(self, dmgr, ref_period, external_clock=False, def __init__(self, dmgr, ref_period, external_clock=False,
ref_multiplier=8, comm_device="comm"): ref_multiplier=8, comm_device="comm"):
self.ref_period = ref_period self.ref_period = ref_period

10
artiq/coredevice/dds.py
View File

@ -29,6 +29,8 @@ def dds_batch_exit() -> TNone:
class _BatchContextManager: class _BatchContextManager:
kernel_constant_attributes = {'core', 'core_dds'}
def __init__(self, core_dds): def __init__(self, core_dds):
self.core_dds = core_dds self.core_dds = core_dds
self.core = self.core_dds.core self.core = self.core_dds.core
@ -50,6 +52,9 @@ class CoreDDS:
:param sysclk: DDS system frequency. The DDS system clock must be a :param sysclk: DDS system frequency. The DDS system clock must be a
phase-locked multiple of the RTIO clock. phase-locked multiple of the RTIO clock.
""" """
kernel_constant_attributes = {'core', 'sysclk', 'batch'}
def __init__(self, dmgr, sysclk, core_device="core"): def __init__(self, dmgr, sysclk, core_device="core"):
self.core = dmgr.get(core_device) self.core = dmgr.get(core_device)
self.sysclk = sysclk self.sysclk = sysclk
@ -82,6 +87,11 @@ class _DDSGeneric:
:param bus: name of the DDS bus device that this DDS is connected to. :param bus: name of the DDS bus device that this DDS is connected to.
:param channel: channel number of the DDS device to control. :param channel: channel number of the DDS device to control.
""" """
kernel_constant_attributes = {
'core', 'core_dds', 'bus_channel', 'channel', 'pow_width'
}
def __init__(self, dmgr, bus_channel, channel, core_dds_device="core_dds"): def __init__(self, dmgr, bus_channel, channel, core_dds_device="core_dds"):
self.core_dds = dmgr.get(core_dds_device) self.core_dds = dmgr.get(core_dds_device)
self.core = self.core_dds.core self.core = self.core_dds.core