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ad9912/10: add a bit more slack to init()

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Robert Jördens 2018-02-26 18:53:39 +00:00 committed by Robert Jordens
parent f97163cdee
commit 5046d6a529
2 changed files with 8 additions and 8 deletions
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6
artiq/coredevice/ad9910.py
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@ -132,15 +132,15 @@ class AD9910:
"""
# Set SPI mode
self.write32(_AD9910_REG_CFR1, 0x00000002)
self.cpld.io_update.pulse(1*us)
self.cpld.io_update.pulse(2*us)
# Use the AUX DAC setting to identify and confirm presence
aux_dac = self.read32(_AD9910_REG_AUX_DAC)
if aux_dac & 0xff != 0x7f:
raise ValueError("Urukul AD9910 AUX_DAC mismatch")
delay(20*us) # slack
delay(50*us) # slack
# Configure PLL settings and bring up PLL
self.write32(_AD9910_REG_CFR2, 0x01400020)
self.cpld.io_update.pulse(1*us)
self.cpld.io_update.pulse(2*us)
cfr3 = (0x0807c100 | (self.pll_vco << 24) |
(self.pll_cp << 19) | (self.pll_n << 1))
self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset

10
artiq/coredevice/ad9912.py
View File

@ -92,20 +92,20 @@ class AD9912:
"""
# SPI mode
self.write(AD9912_SER_CONF, 0x99, length=1)
self.cpld.io_update.pulse(1*us)
self.cpld.io_update.pulse(2*us)
# Verify chip ID and presence
prodid = self.read(AD9912_PRODIDH, length=2)
if (prodid != 0x1982) and (prodid != 0x1902):
raise ValueError("Urukul AD9912 product id mismatch")
delay(30*us)
delay(50*us)
# HSTL power down, CMOS power down
self.write(AD9912_PWRCNTRL1, 0x80, length=1)
self.cpld.io_update.pulse(1*us)
self.cpld.io_update.pulse(2*us)
self.write(AD9912_N_DIV, self.pll_n//2 - 2, length=1)
self.cpld.io_update.pulse(1*us)
self.cpld.io_update.pulse(2*us)
# I_cp = 375 µA, VCO high range
self.write(AD9912_PLLCFG, 0b00000101, length=1)
self.cpld.io_update.pulse(1*us)
self.cpld.io_update.pulse(2*us)
@kernel
def set_att_mu(self, att):