forked from M-Labs/artiq
ad9912/10: add a bit more slack to init()
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@ -132,15 +132,15 @@ class AD9910:
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"""
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# Set SPI mode
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self.write32(_AD9910_REG_CFR1, 0x00000002)
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self.cpld.io_update.pulse(1*us)
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self.cpld.io_update.pulse(2*us)
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# Use the AUX DAC setting to identify and confirm presence
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aux_dac = self.read32(_AD9910_REG_AUX_DAC)
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if aux_dac & 0xff != 0x7f:
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raise ValueError("Urukul AD9910 AUX_DAC mismatch")
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delay(20*us) # slack
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delay(50*us) # slack
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# Configure PLL settings and bring up PLL
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self.write32(_AD9910_REG_CFR2, 0x01400020)
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self.cpld.io_update.pulse(1*us)
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self.cpld.io_update.pulse(2*us)
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cfr3 = (0x0807c100 | (self.pll_vco << 24) |
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(self.pll_cp << 19) | (self.pll_n << 1))
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self.write32(_AD9910_REG_CFR3, cfr3 | 0x400) # PFD reset
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@ -92,20 +92,20 @@ class AD9912:
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"""
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# SPI mode
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self.write(AD9912_SER_CONF, 0x99, length=1)
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self.cpld.io_update.pulse(1*us)
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self.cpld.io_update.pulse(2*us)
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# Verify chip ID and presence
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prodid = self.read(AD9912_PRODIDH, length=2)
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if (prodid != 0x1982) and (prodid != 0x1902):
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raise ValueError("Urukul AD9912 product id mismatch")
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delay(30*us)
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delay(50*us)
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# HSTL power down, CMOS power down
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self.write(AD9912_PWRCNTRL1, 0x80, length=1)
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self.cpld.io_update.pulse(1*us)
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self.cpld.io_update.pulse(2*us)
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self.write(AD9912_N_DIV, self.pll_n//2 - 2, length=1)
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self.cpld.io_update.pulse(1*us)
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self.cpld.io_update.pulse(2*us)
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# I_cp = 375 µA, VCO high range
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self.write(AD9912_PLLCFG, 0b00000101, length=1)
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self.cpld.io_update.pulse(1*us)
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self.cpld.io_update.pulse(2*us)
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@kernel
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def set_att_mu(self, att):
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