forked from M-Labs/artiq
phaser: fix coarse mixer register offset
The CMIX bits are bits 12-15 in register 0x0d. This has been checked against the datasheet and verified on hardware. Until now, the bit for CMIX1 was written to CMIX0. The CMIX0 bit was written to a reserved bit. Signed-off-by: Marius Weber <marius.weber@physics.ox.ac.uk>
This commit is contained in:
parent
515cfa7dfb
commit
4fa2028671
|
@ -201,7 +201,7 @@ class DAC34H84:
|
||||||
mmap.append(
|
mmap.append(
|
||||||
(0x0d << 16) |
|
(0x0d << 16) |
|
||||||
(self.cmix_fs8 << 15) | (self.cmix_fs4 << 14) |
|
(self.cmix_fs8 << 15) | (self.cmix_fs4 << 14) |
|
||||||
(self.cmix_fs2 << 12) | (self.cmix_nfs4 << 11) |
|
(self.cmix_fs2 << 13) | (self.cmix_nfs4 << 12) |
|
||||||
(self.qmc_gainb << 0))
|
(self.qmc_gainb << 0))
|
||||||
mmap.append((0x0e << 16) | (self.qmc_gainc << 0))
|
mmap.append((0x0e << 16) | (self.qmc_gainc << 0))
|
||||||
mmap.append(
|
mmap.append(
|
||||||
|
|
Loading…
Reference in New Issue