forked from M-Labs/artiq
drtio: always use NoRetiming on MultiReg inputs
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9bbc6eb0ef
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@ -3,7 +3,7 @@ from operator import xor, or_
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from migen import *
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from migen import *
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from migen.genlib.fsm import *
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from migen.genlib.fsm import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.cdc import MultiReg, NoRetiming
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class Scrambler(Module):
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class Scrambler(Module):
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@ -248,7 +248,9 @@ class LinkLayer(Module):
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rx_remote_rx_ready = Signal()
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rx_remote_rx_ready = Signal()
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rx_link_init = Signal()
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rx_link_init = Signal()
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self.specials += [
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self.specials += [
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NoRetiming(rx.remote_rx_ready),
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MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"),
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MultiReg(rx.remote_rx_ready, rx_remote_rx_ready, "rtio"),
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NoRetiming(rx.link_init),
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MultiReg(rx.link_init, rx_link_init, "rtio")
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MultiReg(rx.link_init, rx_link_init, "rtio")
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]
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]
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@ -1,5 +1,5 @@
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from migen import *
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from migen import *
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from migen.genlib.cdc import MultiReg
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from migen.genlib.cdc import MultiReg, NoRetiming
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from misoc.interconnect.csr import *
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from misoc.interconnect.csr import *
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@ -44,7 +44,10 @@ class RTController(Module):
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self.sync += If(self.kcsrs.counter_update.re,
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self.sync += If(self.kcsrs.counter_update.re,
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self.kcsrs.counter.status.eq(self.counter.value_sys))
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self.kcsrs.counter.status.eq(self.counter.value_sys))
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tsc_correction = Signal(64)
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tsc_correction = Signal(64)
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self.specials += MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction)
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self.specials += [
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NoRetiming(self.kcsrs.tsc_correction.storage),
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MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction)
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]
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self.comb += [
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self.comb += [
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rt_packets.tsc_value.eq(
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rt_packets.tsc_value.eq(
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self.counter.value_rtio + tsc_correction),
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self.counter.value_rtio + tsc_correction),
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