diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py index 6d7dedc01..e77f8db80 100755 --- a/artiq/gateware/targets/kc705.py +++ b/artiq/gateware/targets/kc705.py @@ -467,9 +467,8 @@ class AD9154JESD(Module, AutoCSR): qpll, platform.request("ad9154_jesd", i), fabric_freq) platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate) self.comb += phy.gtx.gtx_init.bypass_phalign.eq(1) # TODO - platform.add_false_path_constraints( - self.cd_jesd.clk, - phy.gtx.cd_tx.clk) + for clk in self.cd_jesd.clk, refclk_pads.p, self.refclk: + platform.add_false_path_constraints(clk, phy.gtx.cd_tx.clk) phys.append(phy) to_jesd = ClockDomainsRenamer("jesd") self.submodules.core = to_jesd(JESD204BCoreTX(phys, settings,