forked from M-Labs/artiq
test: relax test_rtio.test_loopback
With SED there are 8 additional FIFO output stages.
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@ -362,7 +362,7 @@ class CoredeviceTest(ExperimentCase):
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rtt = self.dataset_mgr.get("rtt")
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print(rtt)
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self.assertGreater(rtt, 0*ns)
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self.assertLess(rtt, 60*ns)
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self.assertLess(rtt, 124*ns)
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def test_clock_generator_loopback(self):
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self.execute(ClockGeneratorLoopback)
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