forked from M-Labs/artiq
firmware/ad9154: combine analog and digital delay of hmc7043 for sysref scan
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fe9834bac4
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@ -1,6 +1,6 @@
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use board::{csr, clock};
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use ad9154_reg;
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use hmc830_7043::{hmc7043};
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use hmc830_7043::hmc7043;
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fn spi_setup(dacno: u8) {
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unsafe {
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@ -611,39 +611,39 @@ fn dac_cfg_retry(dacno: u8) -> Result<(), &'static str> {
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fn dac_sysref_cfg(dacno: u8) {
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let mut sync_error: u16 = 0;
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let mut sync_error_last: u16 = 0;
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let mut cphase_min_found: bool = false;
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let mut cphase_min: u8 = 0;
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let mut cphase_max_found: bool = false;
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let mut cphase_max: u8 = 0;
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let mut cphase_opt: u8 = 0;
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let mut phase_min_found: bool = false;
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let mut phase_min: u16 = 0;
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let mut phase_max_found: bool = false;
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let mut phase_max: u16 = 0;
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let mut phase_opt: u16 = 0;
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info!("AD9154-{} SYSREF scan/conf...", dacno);
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for cphase in 0..32 {
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hmc7043::cfg_dac_sysref(dacno, 0, cphase);
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for phase in 0..512 {
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hmc7043::cfg_dac_sysref(dacno, phase);
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clock::spin_us(10000);
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spi_setup(dacno);
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sync_error = ((read(ad9154_reg::SYNC_CURRERR_L) as u16) |
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((read(ad9154_reg::SYNC_CURRERR_H) as u16) << 8))
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& 0x1ff;
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info!(" cphase: {}, sync error: {}", cphase, sync_error);
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info!(" phase: {}, sync error: {}", phase, sync_error);
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if sync_error != 0 {
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if cphase_min_found {
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if phase_min_found {
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if sync_error != sync_error_last {
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cphase_max_found = true;
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cphase_max = cphase - 1;
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phase_max_found = true;
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phase_max = phase - 1;
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break;
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}
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} else {
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cphase_min_found = true;
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cphase_min = cphase;
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phase_min_found = true;
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phase_min = phase;
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}
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}
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sync_error_last = sync_error;
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}
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cphase_opt = cphase_min + (cphase_max-cphase_min)/2;
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info!(" cphase min: {}, cphase max: {}, cphase opt: {}", cphase_min, cphase_max, cphase_opt);
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hmc7043::cfg_dac_sysref(dacno, 0, cphase_opt);
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phase_opt = phase_min + (phase_max-phase_min)/2;
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info!(" phase min: {}, phase max: {}, phase opt: {}", phase_min, phase_max, phase_opt);
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hmc7043::cfg_dac_sysref(dacno, phase_opt);
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}
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pub fn init() -> Result<(), &'static str> {
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@ -250,14 +250,18 @@ pub mod hmc7043 {
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Ok(())
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}
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pub fn cfg_dac_sysref(dacno: u8, aphase: u8, cphase: u8) {
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pub fn cfg_dac_sysref(dacno: u8, phase: u16) {
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spi_setup();
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/* Analog delay resolution: 25ps
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* Digital delay resolution: 1/2 input clock cycle = 416ps for 1.2GHz
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* 16*25ps = 400ps: limit analog delay to 16 steps instead of 32.
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*/
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if dacno == 0 {
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write(0x00D5, aphase);
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write(0x00D6, cphase);
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write(0x00d5, (phase & 0xf) as u8);
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write(0x00d6, ((phase >> 4) & 0x1f) as u8);
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} else if dacno == 1 {
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write(0x00E9, aphase);
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write(0x00EA, cphase);
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write(0x00e9, (phase & 0xf) as u8);
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write(0x00ea, ((phase >> 4) & 0x1f) as u8);
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} else {
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unimplemented!();
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}
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