From 4def5617106d80fe45926b1a0831b4f5a9e4de35 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Wed, 16 Dec 2015 17:36:52 +0800
Subject: [PATCH] targets: integrate RTIO analyzer

---
 artiq/gateware/targets/kc705.py       | 6 +++++-
 artiq/gateware/targets/pipistrello.py | 6 +++---
 2 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 388421dc1..0cfad4faf 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -85,7 +85,8 @@ class _NIST_QCx(MiniSoC, AMPSoC):
         "rtio": None,  # mapped on Wishbone instead
         "rtio_crg": 13,
         "kernel_cpu": 14,
-        "rtio_moninj": 15
+        "rtio_moninj": 15,
+        "rtio_analyzer": 16
     }
     csr_map.update(MiniSoC.csr_map)
     mem_map = {
@@ -138,6 +139,9 @@ TIMESPEC "TSfix_cdc2" = FROM "GRPrio_clk" TO "GRPrsys_clk" TIG;
         self.add_csr_region("rtio", self.mem_map["rtio"] | 0x80000000, 32,
                             rtio_csrs)
 
+        self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio,
+            self.get_native_sdram_if())
+
 
 class NIST_QC1(_NIST_QCx):
     def __init__(self, cpu_type="or1k", **kwargs):
diff --git a/artiq/gateware/targets/pipistrello.py b/artiq/gateware/targets/pipistrello.py
index 6a561f9b7..a417209f4 100755
--- a/artiq/gateware/targets/pipistrello.py
+++ b/artiq/gateware/targets/pipistrello.py
@@ -104,9 +104,9 @@ TIMESPEC "TSfix_ise4" = FROM "GRPsys_clk" TO "GRPrtio_clk" TIG;
 class NIST_QC1(BaseSoC, AMPSoC):
     csr_map = {
         "rtio": None,  # mapped on Wishbone instead
-        "rtio_crg": 13,
-        "kernel_cpu": 14,
-        "rtio_moninj": 15
+        "rtio_crg": 10,
+        "kernel_cpu": 11,
+        "rtio_moninj": 12
     }
     csr_map.update(BaseSoC.csr_map)
     mem_map = {