From 4deeccbead92eea1b5bc3ead3afa9dcc65ce6edb Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 31 Oct 2017 23:13:06 +0800
Subject: [PATCH] coredevice: add shift register driver

---
 artiq/coredevice/shiftreg.py | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 artiq/coredevice/shiftreg.py

diff --git a/artiq/coredevice/shiftreg.py b/artiq/coredevice/shiftreg.py
new file mode 100644
index 000000000..a71d6e217
--- /dev/null
+++ b/artiq/coredevice/shiftreg.py
@@ -0,0 +1,36 @@
+from artiq.language.core import kernel, delay
+from artiq.language.units import us
+
+
+class ShiftReg:
+    """Driver for shift registers/latch combos connected to TTLs"""
+    kernel_invariants = {"dt", "n"}
+    
+    def __init__(self, dmgr, clk, ser, latch, n=32, dt=10*us):
+        self.core = dmgr.get("core")
+        self.clk = dmgr.get(clk)
+        self.ser = dmgr.get(ser)
+        self.latch = dmgr.get(latch)
+        self.n = n
+        self.dt = dt
+
+    @kernel
+    def set(self, data):
+        """Sets the values of the latch outputs. This does not
+        advance the timeline and the waveform is generated before
+        `now`."""
+        delay(-2*(self.n + 1)*self.dt)
+        for i in range(self.n):
+            if (data >> (self.n-i-1)) & 1 == 0:
+                self.ser.off()
+            else:
+                self.ser.on()
+            self.clk.off()
+            delay(self.dt)
+            self.clk.on()
+            delay(self.dt)
+        self.clk.off()
+        self.latch.on()
+        delay(self.dt)
+        self.latch.off()
+        delay(self.dt)