forked from M-Labs/artiq
rtio: add missing import
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@ -4,6 +4,7 @@ from migen.genlib.fifo import *
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from artiq.gateware.rtio import cri
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from artiq.gateware.rtio import cri
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from artiq.gateware.rtio import rtlink
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from artiq.gateware.rtio import rtlink
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from artiq.gateware.rtio.cdc import *
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__all__ = ["InputCollector"]
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__all__ = ["InputCollector"]
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