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phaser: fail init() if frame timestamp measurement times out

Signed-off-by: Etienne Wodey <etienne.wodey@aqt.eu>
This commit is contained in:
Etienne Wodey 2021-09-03 10:58:11 +02:00
parent 075cb26dd7
commit 4d7bd3ee32
2 changed files with 4 additions and 3 deletions

View File

@ -18,7 +18,7 @@ Highlights:
- Improved documentation
- Expose the DAC coarse mixer and ``sif_sync``
- Exposes upconverter calibration and enabling/disabling of upconverter LO & RF outputs.
- Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_timestamp()``)
- Add helpers to align Phaser updates to the RTIO timeline (``get_next_frame_mu()``)
* ``get()``, ``get_mu()``, ``get_att()``, and ``get_att_mu()`` functions added for AD9910 and AD9912
* New hardware support:
- HVAMP_8CH 8 channel HV amplifier for Fastino / Zotino

View File

@ -2,7 +2,6 @@ from numpy import int32, int64
from artiq.language.core import kernel, delay_mu, delay
from artiq.coredevice.rtio import rtio_output, rtio_input_data, rtio_input_timestamp
from artiq.coredevice.core import rtio_get_counter
from artiq.language.units import us, ns, ms, MHz
from artiq.language.types import TInt32
from artiq.coredevice.dac34h84 import DAC34H84
@ -202,6 +201,8 @@ class Phaser:
# determine the origin for frame-aligned timestamps
self.measure_frame_timestamp()
if self.frame_tstamp < 0:
raise ValueError("frame timestamp measurement timed out")
# reset
self.set_cfg(dac_resetb=0, dac_sleep=1, dac_txena=0,
@ -482,7 +483,7 @@ class Phaser:
See `get_next_frame_mu()`.
"""
rtio_output(self.channel_base << 8, 0) # read any register
self.frame_tstamp = rtio_input_timestamp(rtio_get_counter() + 125_000, self.channel_base)
self.frame_tstamp = rtio_input_timestamp(now_mu() + 4 * self.t_frame, self.channel_base)
delay(100 * us)
@kernel