From 4d42df2a7c831c94ca16d8587ba86792d3dc4198 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 15 Feb 2018 20:32:58 +0800 Subject: [PATCH] kasli: set up Si5324 in standalone operation --- artiq/firmware/runtime/main.rs | 15 ++++++++++++++- artiq/gateware/targets/kasli.py | 7 +++++++ 2 files changed, 21 insertions(+), 1 deletion(-) diff --git a/artiq/firmware/runtime/main.rs b/artiq/firmware/runtime/main.rs index bb18e7dbf..4e4011e40 100644 --- a/artiq/firmware/runtime/main.rs +++ b/artiq/firmware/runtime/main.rs @@ -110,7 +110,20 @@ fn startup() { #[cfg(si5324_free_running)] fn setup_si5324_free_running() { - // 150MHz output (hardcoded) + // 125MHz output, from 10MHz CLKIN2 reference + #[cfg(all(rtio_frequency = "125.0", si5324_ext_ref))] + const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings + = board_artiq::si5324::FrequencySettings { + n1_hs : 10, + nc1_ls : 4, + n2_hs : 10, + n2_ls : 300, + n31 : 75, + n32 : 6, + bwsel : 10 + }; + // 150MHz output, from crystal + #[cfg(all(rtio_frequency = "150.0", not(si5324_ext_ref)))] const SI5324_SETTINGS: board_artiq::si5324::FrequencySettings = board_artiq::si5324::FrequencySettings { n1_hs : 9, diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 7684a8f1b..72b147064 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -104,6 +104,8 @@ class _StandaloneBase(MiniSoC, AMPSoC): self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) self.csr_devices.append("i2c") self.config["I2C_BUS_COUNT"] = 1 + self.config["HAS_SI5324"] = None + self.config["SI5324_SOFT_RESET"] = None def add_rtio(self, rtio_channels): self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk) @@ -227,6 +229,10 @@ class Opticlock(_StandaloneBase): def __init__(self, **kwargs): _StandaloneBase.__init__(self, **kwargs) + self.config["SI5324_FREE_RUNNING"] = None + self.config["SI5324_EXT_REF"] = None + self.config["RTIO_FREQUENCY"] = "125.0" + platform = self.platform platform.add_extension(_dio("eem0")) platform.add_extension(_dio("eem1")) @@ -318,6 +324,7 @@ class Master(MiniSoC, AMPSoC): self.config["HAS_SI5324"] = None self.config["SI5324_SOFT_RESET"] = None self.config["SI5324_FREE_RUNNING"] = None + self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.comb += platform.request("sfp_ctl", 2).tx_disable.eq(0) self.submodules.transceiver = gtp_7series.GTP(