forked from M-Labs/artiq
doc: update flterm instructions. Closes #346
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@ -283,8 +283,7 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
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* Check that the board boots by running a serial terminal program (you may need to press its FPGA reconfiguration button or power-cycle it to load the gateware bitstream that was newly written into the flash): ::
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$ make -C ~/artiq-dev/misoc/tools # do only once
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$ ~/artiq-dev/misoc/tools/flterm --port /dev/ttyUSB1
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$ flterm /dev/ttyUSB1
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MiSoC BIOS http://m-labs.hk
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[...]
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Booting from flash...
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@ -292,6 +291,8 @@ These steps are required to generate gateware bitstream (``.bit``) files, build
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Executing booted program.
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ARTIQ runtime built <date/time>
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.. note:: flterm is part of MiSoC. If you installed MiSoC with ``setup.py develop --user``, the flterm launcher is in ``~/.local/bin``.
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The communication parameters are 115200 8-N-1. Ensure that your user has access
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to the serial device (``sudo adduser $USER dialout`` assuming standard setup).
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