forked from M-Labs/artiq
ad9910: add io_update alignment measurement
for #1143 Signed-off-by: Robert Jördens <rj@quartiq.de>
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7b92282012
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@ -298,8 +298,8 @@ class AD9910:
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slack and stability.
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It starts scanning delays around :attr:`sync_delay_seed` (see the
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device database arguments and :meth:`__init__`) at maximum validation window
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size and decreases the window size until a valid delay is found.
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device database arguments and :class:`AD9910`) at maximum validation
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window size and decreases the window size until a valid delay is found.
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:return: Tuple of optimal delay and window size.
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"""
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@ -332,3 +332,42 @@ class AD9910:
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delay(40*us) # slack
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return in_delay, window
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raise ValueError("no valid window/delay")
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@kernel
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def measure_io_update_alignment(self, io_up_delay):
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"""Use the digital ramp generator to locate the alignment between
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IO_UPDATE and SYNC_CLK.
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The ramp generator is set up to a linear frequency ramp
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(dFTW/t_SYNC_CLK=1) and started at a RTIO timestamp.
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After scanning the alignment, an IO_UPDATE delay midway between two
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edges should be chosen.
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:return: odd/even SYNC_CLK cycle indicator
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"""
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# set up DRG
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# DRG ACC autoclear and LRR on io update
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self.write32(_AD9910_REG_CFR1, 0x0000c002)
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# DRG -> FTW, DRG enable
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self.write32(_AD9910_REG_CFR2, 0x01090000)
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# no limits
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self.write64(_AD9910_REG_DRAMPL, -1, 0)
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# DRCTL=0, dt=1 t_SYNC_CLK
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self.write32(_AD9910_REG_DRAMPR, 0x00010000)
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# dFTW = 1, (work around negative slope)
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self.write64(_AD9910_REG_DRAMPS, -1, 0)
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at_mu(now_mu() + 0x10 & ~0xf) # align to RTIO/2
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self.cpld.io_update.pulse_mu(8)
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# disable DRG autoclear and LRR on io_update
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self.write32(_AD9910_REG_CFR1, 0x00000002)
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# stop DRG
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self.write64(_AD9910_REG_DRAMPS, 0, 0)
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at_mu((now_mu() + 0x10 & ~0xf) + io_up_delay) # delay
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self.cpld.io_update.pulse_mu(32 - io_up_delay) # realign
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ftw = self.read32(_AD9910_REG_FTW) # read out effective FTW
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delay(100*us) # slack
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# disable DRG
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self.write32(_AD9910_REG_CFR2, 0x01010000)
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self.cpld.io_update.pulse_mu(8)
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return ftw & 1
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