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drtio: add clock constraints

This commit is contained in:
Sebastien Bourdeauducq 2016-12-03 22:17:29 +08:00
parent 6353f6d590
commit 4b97b9f8ce
3 changed files with 10 additions and 2 deletions
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8
artiq/gateware/drtio/transceiver/gtx_7series.py
View File

@ -11,8 +11,9 @@ class GTX_20X(Module):
# The transceiver clock on clock_pads must be at the RTIO clock # The transceiver clock on clock_pads must be at the RTIO clock
# frequency when clock_div2=False, and 2x that frequency when # frequency when clock_div2=False, and 2x that frequency when
# clock_div2=True. # clock_div2=True.
def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq, def __init__(self, platform,
clock_div2=False): clock_pads, tx_pads, rx_pads,
sys_clk_freq, clock_div2=False):
self.submodules.encoder = ClockDomainsRenamer("rtio")( self.submodules.encoder = ClockDomainsRenamer("rtio")(
Encoder(2, True)) Encoder(2, True))
self.decoders = [ClockDomainsRenamer("rtio_rx")( self.decoders = [ClockDomainsRenamer("rtio_rx")(
@ -175,6 +176,9 @@ class GTX_20X(Module):
Instance("BUFG", i_I=rxoutclk, o_O=self.cd_rtio_rx.clk), Instance("BUFG", i_I=rxoutclk, o_O=self.cd_rtio_rx.clk),
AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched) AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched)
] ]
platform.add_period_constraint(txoutclk, 1e9/self.rtio_clk_freq)
platform.add_period_constraint(rxoutclk, 1e9/self.rtio_clk_freq)
platform.add_false_path_constraints(txoutclk, rxoutclk)
self.comb += [ self.comb += [
txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1])), txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1])),

2
artiq/gateware/targets/kc705_drtio_master.py
View File

@ -59,6 +59,7 @@ class Master(MiniSoC, AMPSoC):
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
# simple TTLs # simple TTLs
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10( self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
platform=platform,
clock_pads=platform.request("sgmii_clock"), clock_pads=platform.request("sgmii_clock"),
tx_pads=tx_pads, tx_pads=tx_pads,
rx_pads=rx_pads, rx_pads=rx_pads,
@ -69,6 +70,7 @@ class Master(MiniSoC, AMPSoC):
# with SAWG on local RTIO and AD9154-FMC-EBZ # with SAWG on local RTIO and AD9154-FMC-EBZ
platform.register_extension(fmc_clock_io) platform.register_extension(fmc_clock_io)
self.submodules.transceiver = gtx_7series.GTX_3G( self.submodules.transceiver = gtx_7series.GTX_3G(
platform=platform,
clock_pads=platform.request("ad9154_refclk"), clock_pads=platform.request("ad9154_refclk"),
tx_pads=tx_pads, tx_pads=tx_pads,
rx_pads=rx_pads, rx_pads=rx_pads,

2
artiq/gateware/targets/kc705_drtio_satellite.py
View File

@ -165,6 +165,7 @@ class Satellite(Module):
# GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock
# simple TTLs # simple TTLs
self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10( self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10(
platform=platform,
clock_pads=platform.request("sgmii_clock"), clock_pads=platform.request("sgmii_clock"),
tx_pads=tx_pads, tx_pads=tx_pads,
rx_pads=rx_pads, rx_pads=rx_pads,
@ -175,6 +176,7 @@ class Satellite(Module):
# with SAWG on local RTIO and AD9154-FMC-EBZ # with SAWG on local RTIO and AD9154-FMC-EBZ
platform.register_extension(fmc_clock_io) platform.register_extension(fmc_clock_io)
self.submodules.transceiver = gtx_7series.GTX_3G( self.submodules.transceiver = gtx_7series.GTX_3G(
platform=platform,
clock_pads=platform.request("ad9154_refclk"), clock_pads=platform.request("ad9154_refclk"),
tx_pads=tx_pads, tx_pads=tx_pads,
rx_pads=rx_pads, rx_pads=rx_pads,