From 4b97b9f8ce1d55e9b66f489f2ded235d7fbdf392 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sat, 3 Dec 2016 22:17:29 +0800 Subject: [PATCH] drtio: add clock constraints --- artiq/gateware/drtio/transceiver/gtx_7series.py | 8 ++++++-- artiq/gateware/targets/kc705_drtio_master.py | 2 ++ artiq/gateware/targets/kc705_drtio_satellite.py | 2 ++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/drtio/transceiver/gtx_7series.py b/artiq/gateware/drtio/transceiver/gtx_7series.py index 6c0a3e789..2c5897a91 100644 --- a/artiq/gateware/drtio/transceiver/gtx_7series.py +++ b/artiq/gateware/drtio/transceiver/gtx_7series.py @@ -11,8 +11,9 @@ class GTX_20X(Module): # The transceiver clock on clock_pads must be at the RTIO clock # frequency when clock_div2=False, and 2x that frequency when # clock_div2=True. - def __init__(self, clock_pads, tx_pads, rx_pads, sys_clk_freq, - clock_div2=False): + def __init__(self, platform, + clock_pads, tx_pads, rx_pads, + sys_clk_freq, clock_div2=False): self.submodules.encoder = ClockDomainsRenamer("rtio")( Encoder(2, True)) self.decoders = [ClockDomainsRenamer("rtio_rx")( @@ -175,6 +176,9 @@ class GTX_20X(Module): Instance("BUFG", i_I=rxoutclk, o_O=self.cd_rtio_rx.clk), AsyncResetSynchronizer(self.cd_rtio_rx, rx_reset_deglitched) ] + platform.add_period_constraint(txoutclk, 1e9/self.rtio_clk_freq) + platform.add_period_constraint(rxoutclk, 1e9/self.rtio_clk_freq) + platform.add_false_path_constraints(txoutclk, rxoutclk) self.comb += [ txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1])), diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index 8fb5cd1a4..4f0ed088b 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -59,6 +59,7 @@ class Master(MiniSoC, AMPSoC): # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock # simple TTLs self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10( + platform=platform, clock_pads=platform.request("sgmii_clock"), tx_pads=tx_pads, rx_pads=rx_pads, @@ -69,6 +70,7 @@ class Master(MiniSoC, AMPSoC): # with SAWG on local RTIO and AD9154-FMC-EBZ platform.register_extension(fmc_clock_io) self.submodules.transceiver = gtx_7series.GTX_3G( + platform=platform, clock_pads=platform.request("ad9154_refclk"), tx_pads=tx_pads, rx_pads=rx_pads, diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py index 7a882ab94..f331c6dca 100755 --- a/artiq/gateware/targets/kc705_drtio_satellite.py +++ b/artiq/gateware/targets/kc705_drtio_satellite.py @@ -165,6 +165,7 @@ class Satellite(Module): # GTX_1000BASE_BX10 Ethernet compatible, 62.5MHz RTIO clock # simple TTLs self.submodules.transceiver = gtx_7series.GTX_1000BASE_BX10( + platform=platform, clock_pads=platform.request("sgmii_clock"), tx_pads=tx_pads, rx_pads=rx_pads, @@ -175,6 +176,7 @@ class Satellite(Module): # with SAWG on local RTIO and AD9154-FMC-EBZ platform.register_extension(fmc_clock_io) self.submodules.transceiver = gtx_7series.GTX_3G( + platform=platform, clock_pads=platform.request("ad9154_refclk"), tx_pads=tx_pads, rx_pads=rx_pads,